[PATCH 1/3] drm/amdgpu: add sdma debug parameter
Alex Deucher <[email protected]>
| Newsgroups | org.freedesktop.lists.amd-gfx |
|---|---|
| Message-ID | <[email protected]> |
From: Likun Gao <[email protected]> Add parameter to switch sdma RB CMD for sdma v7.1. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 + drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 395235272339b..53738b40c97f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -148,6 +148,7 @@ enum AMDGPU_DEBUG_MASK { AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12), + AMDGPU_DEBUG_SDMA_RB_CMD = BIT(13), }; unsigned int amdgpu_vram_limit = UINT_MAX; @@ -2301,6 +2302,11 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev) pr_info("debug: IP block soft reset disabled\n"); adev->debug_disable_ip_block_soft_reset = true; } + + if (amdgpu_debug_mask & AMDGPU_DEBUG_SDMA_RB_CMD) { + pr_info("debug: enable SDMA RB command switch\n"); + adev->sdma.sdma_debug = true; + } } static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index 4f4e56022c970..671cfbb67b7a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h @@ -103,6 +103,7 @@ struct amdgpu_sdma { int num_instances; uint32_t sdma_mask; + bool sdma_debug; union { int num_inst_per_aid; int num_inst_per_xcc; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index e9a3bcfd7775c..645f8b446652b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -1365,6 +1365,22 @@ static int sdma_v7_1_sw_fini(struct amdgpu_ip_block *ip_block) return 0; } +#define regSDMA0_SDMA_FE_CNTL0 0x10 +#define regSDMA0_SDMA_FE_CNTL0_BASE_IDX 0 +static void sdma_v7_1_rb_cmd_switch(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + int i, fe_cntl; + + if (adev->sdma.sdma_debug) { + for_each_inst(i, inst_mask) { + fe_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FE_CNTL0)); + fe_cntl &= 0x7fffffff; + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FE_CNTL0), fe_cntl); + } + } +} + static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1373,6 +1389,8 @@ static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block) inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); + sdma_v7_1_rb_cmd_switch(adev, inst_mask); + r = sdma_v7_1_inst_start(adev, inst_mask); if (r) return r; -- 2.55.0