[PATCH 1/4] drm/amd/ras: add supported aca blocks mapping
Alex Deucher <[email protected]>
| Newsgroups | org.freedesktop.lists.amd-gfx |
|---|---|
| Message-ID | <[email protected]> |
From: "Stanley.Yang" <[email protected]> Add dacee_be, ucie_pcs, lsdma aca blocks mapping, add pcs_xgmi aca block info. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/ras/core/aca.h | 3 ++ drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c | 54 +++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/core/aca.h b/drivers/gpu/drm/amd/ras/core/aca.h index 759119bed870c..e428bf53f3ea8 100644 --- a/drivers/gpu/drm/amd/ras/core/aca.h +++ b/drivers/gpu/drm/amd/ras/core/aca.h @@ -71,6 +71,9 @@ enum aca_ecc_hwip { ACA_ECC_HWIP__MMHUB, ACA_ECC_HWIP__MPIFOE, ACA_ECC_HWIP__PCIE_PL, + ACA_ECC_HWIP__DACC_BE, + ACA_ECC_HWIP__UCIE_PCS, + ACA_ECC_HWIP__LSDMA, ACA_ECC_HWIP_COUNT, }; diff --git a/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c b/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c index fe3942f54afc5..2c8dcc5886f3c 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c +++ b/drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c @@ -50,6 +50,9 @@ static const u32 sdma_aca_types[] = {0x00}; static const u32 mmhub_aca_types[] = {0x00}; static const u32 mpifoe_aca_types[] = {0x00}; static const u32 pcie_pl_aca_types[] = {0x00}; +static const u32 dacc_be_aca_types[] = {0x00}; +static const u32 ucie_pcs_aca_types[] = {0x00}; +static const u32 lsdma_aca_types[] = {0x00}; static struct ras_aca_hwip_v5 aca_hwip_maps[] = { ACA_HWIP_MAP(SMU, 0x01, smu_aca_types), @@ -62,6 +65,9 @@ static struct ras_aca_hwip_v5 aca_hwip_maps[] = { ACA_HWIP_MAP(MMHUB, 0x73, mmhub_aca_types), ACA_HWIP_MAP(MPIFOE, 0x1FD, mpifoe_aca_types), ACA_HWIP_MAP(PCIE_PL, 0x1E1, pcie_pl_aca_types), + ACA_HWIP_MAP(DACC_BE, 0x164, dacc_be_aca_types), + ACA_HWIP_MAP(UCIE_PCS, 0x16C, ucie_pcs_aca_types), + ACA_HWIP_MAP(LSDMA, 0x346, lsdma_aca_types), }; static void aca_decode_bank_info(struct aca_block *aca_blk, @@ -344,6 +350,50 @@ static const struct aca_block_info aca_v5_0_pcie_pl = { }, }; +static const struct aca_block_info aca_v5_0_dacc_be = { + .name = "dacc_be", + .ras_block_id = RAS_BLOCK_ID__DACC_BE, + .hwip = ACA_ECC_HWIP__DACC_BE, + .mask = ACA_ERROR__UE_MASK | ACA_ERROR__CE_MASK, + .bank_ops = { + .bank_match = aca_match_bank_default, + .bank_parse = aca_parse_bank_default, + }, +}; + +static const struct aca_block_info aca_v5_0_ucie_pcs = { + .name = "ucie_pcs", + .ras_block_id = RAS_BLOCK_ID__UCIE_PCS, + .hwip = ACA_ECC_HWIP__UCIE_PCS, + .mask = ACA_ERROR__UE_MASK | ACA_ERROR__CE_MASK, + .bank_ops = { + .bank_match = aca_match_bank_default, + .bank_parse = aca_parse_bank_default, + }, +}; + +static const struct aca_block_info aca_v5_0_lsdma = { + .name = "lsdma", + .ras_block_id = RAS_BLOCK_ID__LSDMA, + .hwip = ACA_ECC_HWIP__LSDMA, + .mask = ACA_ERROR__UE_MASK | ACA_ERROR__CE_MASK, + .bank_ops = { + .bank_match = aca_match_bank_default, + .bank_parse = aca_parse_bank_default, + }, +}; + +static const struct aca_block_info aca_v5_0_pcs_xgmi = { + .name = "pcs_xgmi", + .ras_block_id = RAS_BLOCK_ID__PCS_XGMI, + .hwip = ACA_ECC_HWIP__PCS_XGMI, + .mask = ACA_ERROR__UE_MASK | ACA_ERROR__CE_MASK, + .bank_ops = { + .bank_match = aca_match_bank_default, + .bank_parse = aca_parse_bank_default, + }, +}; + static const struct aca_block_info *aca_block_info_v5_0[] = { &aca_v5_0_umc, &aca_v5_0_gfx, @@ -351,6 +401,10 @@ static const struct aca_block_info *aca_block_info_v5_0[] = { &aca_v5_0_mmhub, &aca_v5_0_xgmi, &aca_v5_0_pcie_pl, + &aca_v5_0_dacc_be, + &aca_v5_0_ucie_pcs, + &aca_v5_0_lsdma, + &aca_v5_0_pcs_xgmi, }; static u64 aca_parse_ras_caps_v5_0(struct ras_core_context *ras_core) -- 2.55.0