[PATCH 22/59] drm/amd/display: Update HDMI link rate and DSC handling for DCN60

Alex Hung <[email protected]>
Newsgroups org.freedesktop.lists.amd-gfx
Message-ID <[email protected]> 
From: Relja Vojvodic <[email protected]>

[WHAT]
- Updated switch cases to handle new link rates
- Reverted set stream attribute behaviour to DCN401 version to unblock
  DSC on DCN 60

Reviewed-by: Dillon Varone <[email protected]>
Signed-off-by: Relja Vojvodic <[email protected]>
Signed-off-by: Alex Hung <[email protected]>
---
 .../drm/amd/display/dc/core/dc_link_exports.c |   3 +-
 .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c  |  18 ++-
 .../drm/amd/display/dc/dml/dml1_frl_cap_chk.c |   8 +-
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   |   8 ++
 .../drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c  |   4 +-
 .../hpo/dcn60/dcn60_hpo_frl_stream_encoder.c  | 131 +-----------------
 .../drm/amd/display/dc/link/link_detection.c  |   2 +
 7 files changed, 37 insertions(+), 137 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index ba1b46d3a13e..fef857c7336b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -368,8 +368,7 @@ enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc
 
 		if (frl_link_settings->frl_link_rate == HDMI_FRL_LINK_RATE_DISABLE)
 			return DC_LINK_ENCODING_HDMI_TMDS;
-		else if (frl_link_settings->frl_link_rate >= HDMI_FRL_LINK_RATE_3GBPS &&
-				frl_link_settings->frl_link_rate <= HDMI_FRL_LINK_RATE_12GBPS)
+		else if (frl_link_settings->frl_link_rate >= HDMI_FRL_LINK_RATE_3GBPS)
 			return DC_LINK_ENCODING_HDMI_FRL;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index 6f5a11d37899..b8e5985f9307 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -774,12 +774,19 @@ void hpo_fpu_enc3_validate_hdmi_frl_output_link(struct hpo_frl_stream_encoder *e
 		frl_params->r_bit_nominal = 8.0e9;
 		break;
 	case HDMI_FRL_LINK_RATE_10GBPS:
-	default:
 		frl_params->r_bit_nominal = 10.0e9;
 		break;
 	case HDMI_FRL_LINK_RATE_12GBPS:
 		frl_params->r_bit_nominal = 12.0e9;
 		break;
+	case HDMI_FRL_LINK_RATE_16GBPS:
+		frl_params->r_bit_nominal = 16.0e9;
+		break;
+	case HDMI_FRL_LINK_RATE_20GBPS:
+		frl_params->r_bit_nominal = 20.0e9;
+		break;
+	default:
+		break;
 	}
 
 	if (timing->flags.DSC &&
@@ -802,12 +809,19 @@ void hpo_fpu_enc3_validate_hdmi_frl_output_link(struct hpo_frl_stream_encoder *e
 			frl_params->r_bit_nominal = 8.0e9;
 			break;
 		case HDMI_FRL_LINK_RATE_10GBPS:
-		default:
 			frl_params->r_bit_nominal = 10.0e9;
 			break;
 		case HDMI_FRL_LINK_RATE_12GBPS:
 			frl_params->r_bit_nominal = 12.0e9;
 			break;
+		case HDMI_FRL_LINK_RATE_16GBPS:
+			frl_params->r_bit_nominal = 16.0e9;
+			break;
+		case HDMI_FRL_LINK_RATE_20GBPS:
+			frl_params->r_bit_nominal = 20.0e9;
+			break;
+		default:
+			break;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_frl_cap_chk.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_frl_cap_chk.c
index da2c92e5c02f..bfbc64163d01 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml1_frl_cap_chk.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_frl_cap_chk.c
@@ -680,12 +680,18 @@ static double calculate_compressed_active_time(uint32_t h_active,
 		r_bit_nominal = 8.0e9;
 		break;
 	case FRL_LINK_RATE_10GBPS:
-	default:
 		r_bit_nominal = 10.0e9;
 		break;
 	case FRL_LINK_RATE_12GBPS:
 		r_bit_nominal = 12.0e9;
 		break;
+	case FRL_LINK_RATE_16GBPS:
+		r_bit_nominal = 16.0e9;
+		break;
+	case FRL_LINK_RATE_20GBPS:
+	default:
+		r_bit_nominal = 20.0e9;
+		break;
 	}
 
 	f_tb_average = pix_clk / (h_active + h_blank)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index ba4988118c68..febb6af43827 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -1290,6 +1290,14 @@ static bool convert_bandwidth_to_frl_params(
 		*num_lanes = 4;
 		*frl_rate = 12000;
 		break;
+	case 64000000:
+		*num_lanes = 4;
+		*frl_rate = 16000;
+		break;
+	case 80000000:
+		*num_lanes = 4;
+		*frl_rate = 20000;
+		break;
 	default:
 		return false;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c
index 0cfedd4268c6..5bb4ed1d1ba7 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c
@@ -60,7 +60,7 @@ void dsc60_construct(struct dcn60_dsc *dsc,
 	dsc->dsc_shift = dsc_shift;
 	dsc->dsc_mask = dsc_mask;
 
-	dsc->max_image_width = 5184;
+	dsc->max_image_width = 5760;
 }
 
 static void dsc60_init_reg_values(struct dsc60_reg_values *reg_vals)
@@ -181,7 +181,7 @@ static bool dsc60_prepare_config(const struct dsc_config *dsc_cfg, struct dsc60_
 
 	// TODO: in addition to validating slice height (pic height must be divisible by slice height),
 	// see what happens when the same condition doesn't apply for slice_width/pic_width.
-	dsc_reg_vals->pps.slice_width = (u16)(dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h);
+	dsc_reg_vals->pps.slice_width = (u16)((dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h);
 	dsc_reg_vals->pps.slice_height = (u16)(dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v);
 
 	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn60/dcn60_hpo_frl_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn60/dcn60_hpo_frl_stream_encoder.c
index 3f3704b68021..bded65896ef5 100644
--- a/drivers/gpu/drm/amd/display/dc/hpo/dcn60/dcn60_hpo_frl_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn60/dcn60_hpo_frl_stream_encoder.c
@@ -32,135 +32,6 @@
 
 #define VBI_LINE_0 0
 
-/* setup stream encoder in hdmi mode */
-/* Precondition: link is trained */
-static void hpo_enc60_set_hdmi_stream_attribute(
-	struct hpo_frl_stream_encoder *enc,
-	struct dc_crtc_timing *crtc_timing,
-	struct frl_borrow_params *borrow_params,
-	int odm_combine_num_segments)
-{
-	(void)odm_combine_num_segments;
-	uint32_t h_active;
-	uint32_t h_blank;
-	struct dcn401_hpo_frl_stream_encoder *enc401 = DCN401_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(enc);
-
-	DC_LOG_DEBUG("Entering [%s]\n", __func__);
-
-	/* Configure pixel encoding */
-	switch (crtc_timing->pixel_encoding) {
-	case PIXEL_ENCODING_YCBCR422:
-		REG_UPDATE(HDMI_TB_ENC_PIXEL_FORMAT,
-				HDMI_PIXEL_ENCODING, 1);
-		REG_UPDATE_2(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
-				FIFO_PIXEL_ENCODING_TYPE, 0,
-				FIFO_UNCOMPRESSED_PIXEL_FORMAT, 0);
-		break;
-	case PIXEL_ENCODING_YCBCR420:
-		REG_UPDATE(HDMI_TB_ENC_PIXEL_FORMAT,
-				HDMI_PIXEL_ENCODING, 2);
-		REG_UPDATE_2(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
-				FIFO_PIXEL_ENCODING_TYPE, 0,
-				FIFO_UNCOMPRESSED_PIXEL_FORMAT, 1);
-		break;
-	default:
-		REG_UPDATE(HDMI_TB_ENC_PIXEL_FORMAT,
-				HDMI_PIXEL_ENCODING, 0);
-		REG_UPDATE_2(HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
-				FIFO_PIXEL_ENCODING_TYPE, 0,
-				FIFO_UNCOMPRESSED_PIXEL_FORMAT, 0);
-		break;
-	}
-
-	/* Configure color depth */
-	switch (crtc_timing->display_color_depth) {
-	case COLOR_DEPTH_888:
-		REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
-				HDMI_DEEP_COLOR_DEPTH, 0,
-				HDMI_DEEP_COLOR_ENABLE, 0);
-		break;
-	case COLOR_DEPTH_101010:
-		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
-					HDMI_DEEP_COLOR_DEPTH, 1,
-					HDMI_DEEP_COLOR_ENABLE, 0);
-		} else {
-			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
-					HDMI_DEEP_COLOR_DEPTH, 1,
-					HDMI_DEEP_COLOR_ENABLE, 1);
-		}
-		break;
-	case COLOR_DEPTH_121212:
-		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
-					HDMI_DEEP_COLOR_DEPTH, 2,
-					HDMI_DEEP_COLOR_ENABLE, 0);
-		} else {
-			REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
-					HDMI_DEEP_COLOR_DEPTH, 2,
-					HDMI_DEEP_COLOR_ENABLE, 1);
-		}
-		break;
-	default:
-		break;
-	}
-
-	/* When compression active, CD/PP/Phase field shall be zero in GCP */
-	if (crtc_timing->flags.DSC) {
-		REG_UPDATE_2(HDMI_TB_ENC_PIXEL_FORMAT,
-				HDMI_DEEP_COLOR_DEPTH, 0,
-				HDMI_DEEP_COLOR_ENABLE, 0);
-	}
-
-	/* Configure horizontal active and blank size */
-	h_active = crtc_timing->h_addressable + crtc_timing->h_border_left + crtc_timing->h_border_right;
-	h_blank = crtc_timing->h_total - h_active;
-
-	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ||
-			crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-		h_active /= 2;
-		h_blank /= 2;
-	}
-
-	REG_SET_2(HDMI_TB_ENC_H_ACTIVE_BLANK, 0,
-			HDMI_H_ACTIVE, h_active,
-			HDMI_H_BLANK, h_blank);
-
-	/* Configure borrow parameters */
-	REG_UPDATE(HDMI_TB_ENC_MODE,
-			HDMI_BORROW_MODE, borrow_params->borrow_mode);
-	REG_UPDATE(HDMI_TB_ENC_PACKET_CONTROL,
-			HDMI_MAX_PACKETS_PER_LINE, borrow_params->audio_packets_line);
-	REG_SET_2(HDMI_TB_ENC_HC_ACTIVE_BLANK, 0,
-			HDMI_HC_ACTIVE, borrow_params->hc_active_target,
-			HDMI_HC_BLANK, borrow_params->hc_blank_target);
-
-	/* Enable transmission of General Control packet on every frame */
-	REG_UPDATE_2(HDMI_TB_ENC_VBI_PACKET_CONTROL1,
-		HDMI_GC_CONT, 1,
-		HDMI_GC_SEND, 1);
-
-	/* Disable Audio Content Protection packet transmission */
-	/* TODO: review if this needs to be here */
-	REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_ACP_SEND, 0);
-
-	/* Enable Audio InfoFrame packet transmission. */
-	REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_SEND, 1);
-
-	/* update double-buffered AUDIO_INFO registers immediately */
-//	ASSERT(enc->afmt);
-//	enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
-
-	/* Select line number on which to send Audio InfoFrame packets */
-	REG_UPDATE(HDMI_TB_ENC_VBI_PACKET_CONTROL1, HDMI_AUDIO_INFO_LINE,
-				VBI_LINE_0 + 2);
-
-	/* set HDMI GC AVMUTE */
-	REG_UPDATE(HDMI_TB_ENC_GC_CONTROL, HDMI_GC_AVMUTE, 0);
-
-	DC_LOG_DEBUG("Exiting [%s]\n", __func__);
-}
-
 static void hpo_enc60_audio_mute_control(
 	struct hpo_frl_stream_encoder *enc,
 	bool mute)
@@ -321,7 +192,7 @@ static const struct hpo_frl_stream_encoder_funcs dcn401_str_enc_funcs = {
 	.hdmi_frl_enable		= hpo_enc401_enable,
 	.hdmi_frl_unblank		= hpo_enc401_unblank,
 	.hdmi_frl_blank			= hpo_enc401_blank,
-	.hdmi_frl_set_stream_attribute	= hpo_enc60_set_hdmi_stream_attribute,
+	.hdmi_frl_set_stream_attribute	= hpo_enc401_set_hdmi_stream_attribute,
 	.validate_hdmi_frl_output	= hpo_enc3_validate_hdmi_frl_output,
 	.update_hdmi_info_packets	= hpo_enc401_update_hdmi_info_packets,
 	.stop_hdmi_info_packets		= hpo_enc401_stop_hdmi_info_packets,
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 1384197578ec..12fd4fd24a90 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -995,6 +995,8 @@ static bool should_verify_link_capability_destructively(struct dc_link *link,
 					}
 				}
 			}
+		} else if (link->dc->debug.skip_detection_link_training) {
+			destrictive = false;
 		}
 	}
 
-- 
2.43.0
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