Re: [PATCH v2 3/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing

Thank you for your contribution! Sashiko AI review found 1 potential issue(=
s) to consider:
- [Low] 64-bit division using the '/' operator causes a linker error on 32-=
bit architectures.
--

--- Patch [3]: [PATCH v2 3/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizon=
tal sync timing ---
commit 2e5ea2d668a183af376a6de9dd60e558786a8b7f
Author: Esben Haabendal <[email protected]>

drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing

This commit corrects the horizontal sync timing for the NWL MIPI Host
controller by calculating the hfp, hsa, and hbp in DSI packet payload size =
in
bytes instead of pixel clocks. It implements the calculation based on the
i.MX 8M reference manual while also taking the packet header size into acco=
unt.

> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nw=
l-dsi.c
> index c9af6a3d47e1d..226036d22e3f8 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
[ ... ]
> @@ -317,9 +322,62 @@ static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
>  			      dsi->mode.hdisplay);
>  	}
> =20
> -	nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
> -	nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
> -	nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
> +	pclk_period =3D DIV_ROUND_UP_ULL(PSEC_PER_SEC, dsi->mode.clock * 1000);
> +	DRM_DEV_DEBUG_DRIVER(dsi->dev, "pclk_period: %llu\n", pclk_period);
> +
> +	hs_period =3D DIV_ROUND_UP_ULL(PSEC_PER_SEC, dsi->phy_cfg.mipi_dphy.hs_=
clk_rate);
> +	DRM_DEV_DEBUG_DRIVER(dsi->dev, "hs_period: %llu\n", hs_period);
> +
> +	/*
> +	 * Calculate the bytes needed, according to the RM formula:
> +	 * Time of DPI event =3D time to transmit x number of bytes on the DSI
> +	 * interface
> +	 * dpi_event_size * dpi_pclk_period =3D dsi_bytes * 8 * hs_bit_period /
> +	 * num_lanes
> +	 * =3D=3D=3D>
> +	 * dsi_bytes =3D dpi_event_size * dpi_pclk_period * num_lanes /
> +	 * (8 * hs_bit_period)
> +	 */
> +	hfp =3D hfront_porch * pclk_period * dsi->lanes / (8 * hs_period);
> +	hbp =3D hback_porch * pclk_period * dsi->lanes / (8 * hs_period);
> +	hsa =3D hsync_len * pclk_period * dsi->lanes / (8 * hs_period);

[Severity: Low]
Since hs_period and pclk_period are unsigned long long, does using the dire=
ct
'/' operator for 64-bit division cause a linker error (such as undefined
reference to __udivdi3) when building for 32-bit architectures?

Could this be resolved by using standard kernel 64-bit division macros such=
 as
div64_u64() instead?

--=20
Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260803-nwl-dsi-fi=
[email protected]?part=3D3