Re: [PATCH v4 1/5] gpu: nova-core: correct FRTS vidmem offset calculation

[email protected] Tue, 04 Aug 2026 05:54:40 +0000
Newsgroups org.freedesktop.lists.dri-devel
Message-ID <[email protected]>
Thank you for your contribution! Sashiko AI review found 1 potential issue(=
s) to consider:
- [Medium] The r570-specific 2 MiB alignment for the FRTS vidmem offset is =
incorrectly skipped if the PMU reserved size is zero.
--

--- Patch [1]: [PATCH v4 1/5] gpu: nova-core: correct FRTS vidmem offset ca=
lculation ---
commit 8aa662faea789e52a898638a43d6d0e165669003
Author: Eliot Courtney <[email protected]>

gpu: nova-core: correct FRTS vidmem offset calculation

This commit changes the calculation of the FRTS vidmem offset to use a
per-architecture reserved size plus the PMU reserved size, rather than
relying on coincidental matching with the non-wpr heap size.

> diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs
> index ba4544210e40f..a81b510282829 100644
> --- a/drivers/gpu/nova-core/fsp.rs
> +++ b/drivers/gpu/nova-core/fsp.rs
> @@ -251,20 +251,31 @@ struct FspCotMessage {
>  }
> =20
>  impl FspCotMessage {
> +    /// Computes the FRTS vidmem offset for the Chain-of-Trust message. =
It is measured backwards
> +    /// from the end of the framebuffer.
> +    fn frts_vidmem_offset(hal: &dyn hal::FspHal, fb_layout: &FbLayout) -=
> Result<u64> {
> +        let mut offset =3D u64::from(hal.fb_end_reserved_size());
> +
> +        if fb_layout.pmu_reserved_size !=3D 0 {
> +            offset =3D (offset + u64::from(fb_layout.pmu_reserved_size))
> +                // The 2 MiB alignment is r570-specific.
> +                .align_up(Alignment::new::<SZ_2M>())
> +                .ok_or(EINVAL)?;
> +        }

[Severity: Medium]
If fb_layout.pmu_reserved_size happens to be 0, this bypasses the 2 MiB
alignment entirely.=20

For platforms like GB100 or GB202 where hal.fb_end_reserved_size() is=20
SZ_2M + SZ_128K (which is unaligned), wouldn't this result in an unaligned
FRTS offset and potentially cause FSP boot failures?=20

Should the 2 MiB alignment step be performed unconditionally even when the=
=20
PMU reservation size is 0?

[ ... ]

--=20
Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260804-blackwell-=
[email protected]?part=3D1