[PATCH 23/44] drm/i915/ddi_buf: Add Vswing table for HDMI FRL

From: Suraj Kandpal <[email protected]>

Define Vswing table for HDMI FRL to set the signal levels.
This is done for LT PHY which is Xe3PLPD onwards.

Bspec: 74493
Signed-off-by: Suraj Kandpal <[email protected]>
---
 .../drm/i915/display/intel_ddi_buf_trans.c    | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 4cd1e4d76c7a..e7f40f1a7eac 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -10,6 +10,7 @@
 #include "intel_display_types.h"
 #include "intel_display_utils.h"
 #include "intel_dp.h"
+#include "intel_hdmi.h"
 #include "intel_lt_phy.h"
 
 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
@@ -1164,6 +1165,22 @@ static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
 	{ .lt = { 1, 3, 0, 26, 0 } },
 };
 
+static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_hdmi_frl[] = {
+	{ .lt = { 0, 0, 0, 48, 0  } },
+	{ .lt = { 0, 0, 4, 38, 6  } },
+	{ .lt = { 0, 0, 0, 42, 6  } },
+	{ .lt = { 0, 0, 4, 44, 0  } },
+	{ .lt = { 0, 0, 4, 36, 8  } },
+	{ .lt = { 0, 0, 0, 40, 8  } },
+	{ .lt = { 0, 0, 4, 44, 0  } },
+	{ .lt = { 0, 0, 4, 34, 10 } },
+	{ .lt = { 0, 0, 0, 38, 10 } },
+	{ .lt = { 0, 0, 4, 44, 0  } },
+	{ .lt = { 0, 0, 4, 32, 12 } },
+	{ .lt = { 0, 0, 0, 36, 12 } },
+	{ .lt = { 0, 0, 4, 44, 0  } },
+};
+
 static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
 	.entries = _xe3plpd_lt_trans_dp14,
 	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
@@ -1179,6 +1196,11 @@ static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = {
 	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp),
 };
 
+static const struct intel_ddi_buf_trans xe3plpd_lt_trans_hdmi_frl = {
+	.entries = _xe3plpd_lt_trans_hdmi_frl,
+	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_hdmi_frl),
+};
+
 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
 {
 	return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1780,6 +1802,9 @@ xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
 		return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+		 intel_hdmi_is_frl(crtc_state->port_clock))
+		return intel_get_buf_trans(&xe3plpd_lt_trans_hdmi_frl, n_entries);
 	else
 		return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
 }
-- 
2.50.1