Re: [PATCH v2 0/5] accel/amdxdna: honour the SYNC_BO range

(Resending to the list -- my earlier copy went to Alex alone.)

On 8/13/26 21:54, Alex Deucher wrote:
> PCIe transactions from the device should snoop the CPU's cache.

That is what I assumed too, but it is not what I measure on npu4. Leaving a new input dirty in the CPU and running, the array computes on the previous contents, each out of 20 runs. Flushing that same input and running again, it sees it - so the data does reach the buffer, and something is not picking up the dirty line.

What I cannot square is that ubuf maps with dma_map_sgtable() and nothing else, and on x86 the DMA API no-ops the syncs, so that path looks correct only because SYNC_BO clflushes on top of it.

Is the array expected to snoop on this part? Happy to run whatever would settle it, or to be told what I am measuring wrong.

Taimuraz