Re: [PATCH 1/3] dt-bindings: display: msm: Allow two MDSS power domains
Konrad Dybcio <[email protected]>
| Newsgroups | org.freedesktop.lists.dri-devel,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
On 8/13/26 9:44 AM, Yongxing Mou wrote: > > > On 7/20/2026 4:49 PM, Konrad Dybcio wrote: >> On 7/20/26 10:43 AM, Yongxing Mou wrote: >>> Kaanapali (SM8750) and Glymur use two display power domains. >>> CORE_GDSC powers the main display hardware while INT2_GDSC >>> powers a subset of SSPP blocks. >> >> Can they operate independently? Does INT2_GDSC need to be >> powered on after CORE_GDSC? >> > On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should generally track the same state, except that INT2_GDSC may be powered down when SSPP1 (VIG2/VIG3/DMA5) is unused. > - CORE off, INT2 off > - CORE on, INT2 off > - CORE on, INT2 on >> If so, perhaps changing the clock driver to make CORE a parent >> of INT2 could be the simpler solution >> >> Konrad > That would still need DT and binding changes -- DPU has to reference INT2_GDSC directly to gate it independently, so it can't be hidden in the clock driver. The two GDSCs have independent GDSCR registers with no HW-enforced sequencing, so they appear to be peers rather than parent/child. No, if that was a reasonable change (which I don't know if it is), the genpd core would take care of enabling the parent before the child, since the genpds are intrinsically hierarchical Konrad