Re: [PATCH 1/3] dt-bindings: display: msm: Allow two MDSS power domains

On Mon, Aug 17, 2026 at 04:12:51PM +0200, Konrad Dybcio wrote:
> On 8/13/26 9:44 AM, Yongxing Mou wrote:
> > 
> > 
> > On 7/20/2026 4:49 PM, Konrad Dybcio wrote:
> >> On 7/20/26 10:43 AM, Yongxing Mou wrote:
> >>> Kaanapali (SM8750) and Glymur use two display power domains.
> >>> CORE_GDSC powers the main display hardware while INT2_GDSC
> >>> powers a subset of SSPP blocks.
> >>
> >> Can they operate independently? Does INT2_GDSC need to be
> >> powered on after CORE_GDSC?
> >>
> > On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should generally track the same state, except that INT2_GDSC may be powered down when SSPP1 (VIG2/VIG3/DMA5) is unused.
> >    - CORE off, INT2 off
> >     - CORE on,  INT2 off
> >     - CORE on,  INT2 on
> >> If so, perhaps changing the clock driver to make CORE a parent
> >> of INT2 could be the simpler solution
> >>
> >> Konrad
> > That would still need DT and binding changes -- DPU has to reference INT2_GDSC directly to gate it independently, so it can't be hidden in the clock driver. The two GDSCs have independent GDSCR registers with no HW-enforced sequencing, so they appear to be peers rather than parent/child.
> 
> No, if that was a reasonable change (which I don't know if it is), the
> genpd core would take care of enabling the parent before the child, since
> the genpds are intrinsically hierarchical

That sounds like an interesting quirk, but then I wonder if we end up
spending extra power in cases when only CORE_GDSC is required for the
device

-- 
With best wishes
Dmitry