[PATCH v2] drm/nouveau: Use write-combined maps for coherent

From: Faith Ekstrand <[email protected]>

On Tegra devices, uncached maps traslate to device memory, causing
unaligned accesses by userspace resulting in a SIGBUS. Instead, use
write-combined maps to ensure proper access.

This would also affect discrete cards on any Arm device. It was
determined that discrete cards regardless of cpu arch should use
write-combined maps for coherent anyways. Thus this change is made for
all gpu types.

Signed-off-by: Faith Ekstrand <[email protected]>
Co-developed-by: Aaron Kling <[email protected]>
Signed-off-by: Aaron Kling <[email protected]>
---
Without this change, nouveau can easily hit sigbus errors in the Android
UI rendering via nvk or running vulkan deqp tests on Tegra. Changing
coherent maps to use write-combined stops the crashing.
---
Changes in v2:
- Set write-combined for coherent on all gpu types
- Link to v1: https://lore.kernel.org/r/[email protected]
---
 drivers/gpu/drm/nouveau/nouveau_sgdma.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index fa3b4ebf38a83..2bd0376193aee 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -72,9 +72,7 @@ nouveau_sgdma_create_ttm(struct ttm_buffer_object *bo, uint32_t page_flags)
 	struct nouveau_sgdma_be *nvbe;
 	enum ttm_caching caching;
 
-	if (nvbo->force_coherent)
-		caching = ttm_uncached;
-	else if (drm->agp.bridge)
+	if (nvbo->force_coherent || drm->agp.bridge)
 		caching = ttm_write_combined;
 	else
 		caching = ttm_cached;

---
base-commit: 903c1cf6dff9964e71eda98a39e2e5d442050472
change-id: 20260725-tegra-coherent-wc-19941d1a5a60

Best regards,
-- 
Aaron Kling <[email protected]>