[PATCH 2/2] drm/i915/cdclk: Introduce has_cd2x_pipe_select()
Ville Syrjala <[email protected]>
| Newsgroups | org.freedesktop.lists.intel-gfx,org.freedesktop.lists.intel-xe |
|---|---|
| Organization | Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland |
| Message-ID | <[email protected]> |
From: Ville Syrjälä <[email protected]> We have several open coded checks for the platform's cd2x pipe select capability, each written slightly differently. Move it all into a common has_cd2x_pipe_select() helper. No functional changes as the previous 'DISPLAY_VER < 30' checks were in codepaths that already exclude pre-bxt platforms, and intel_cdclk_can_cd2x_update() already rejects PTL+ via the later HAS_CDCLK_SQUASH() check. Also update the docs for the register bitfield while at it. Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++---- drivers/gpu/drm/i915/display/intel_display_regs.h | 2 +- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 9e5e15b0c4d1..75ada941d113 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2177,6 +2177,11 @@ static bool pll_enable_wa_needed(struct intel_display *display) display->cdclk.hw.vco > 0; } +static bool has_cd2x_pipe_select(struct intel_display *display) +{ + return IS_DISPLAY_VER(display, 10, 20) || display->platform.broxton; +} + static u32 bxt_cdclk_ctl(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) @@ -2190,7 +2195,7 @@ static u32 bxt_cdclk_ctl(struct intel_display *display, val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform); - if (DISPLAY_VER(display) < 30) + if (has_cd2x_pipe_select(display)) val |= bxt_cdclk_cd2x_pipe(display, pipe); /* @@ -2381,7 +2386,7 @@ static void bxt_sanitize_cdclk(struct intel_display *display) * dividers both syncing to an active pipe, or asynchronously * (PIPE_NONE). */ - if (DISPLAY_VER(display) < 30) { + if (has_cd2x_pipe_select(display)) { cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display); cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); } @@ -2579,8 +2584,7 @@ static bool intel_cdclk_can_cd2x_update(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { - /* Older hw doesn't have the capability */ - if (DISPLAY_VER(display) < 10 && !display->platform.broxton) + if (!has_cd2x_pipe_select(display)) return false; /* diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 0f5018482497..1faca3cdaceb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -2788,7 +2788,7 @@ enum skl_power_gate { #define BXT_CDCLK_CD2X_PIPE_MASK REG_GENMASK(21, 20) /* bxt/glk */ #define BXT_CDCLK_CD2X_PIPE(pipe) REG_FIELD_PREP(BXT_CDCLK_CD2X_PIPE_MASK, (pipe)) #define BXT_CDCLK_CD2X_PIPE_NONE REG_FIELD_PREP(BXT_CDCLK_CD2X_PIPE_MASK, 3) -#define ICL_CDCLK_CD2X_PIPE_MASK REG_GENMASK(21, 19) /* icl+ */ +#define ICL_CDCLK_CD2X_PIPE_MASK REG_GENMASK(21, 19) /* icl-lnl */ #define ICL_CDCLK_CD2X_PIPE(pipe) REG_FIELD_PREP(ICL_CDCLK_CD2X_PIPE_MASK, (pipe) << 1) #define ICL_CDCLK_CD2X_PIPE_NONE REG_FIELD_PREP(ICL_CDCLK_CD2X_PIPE_MASK, 7) #define CDCLK_DIVMUX_CD_OVERRIDE REG_BIT(19) /* pre-icl */ -- 2.54.0