[PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks
Michał Grzelak <[email protected]> Tue, 28 Jul 2026 00:21:24 +0200
| Newsgroups | org.freedesktop.lists.intel-gfx,org.freedesktop.lists.intel-xe |
|---|---|
| Organization | Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 |
| Message-ID | <[email protected]> |
Add indentation into SKL_DSSM reference clock macros. Replace bit shifts with REG_GENMASK(). Signed-off-by: Michał Grzelak <[email protected]> --- drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 0f5018482497..0677ca2dde00 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -1779,10 +1779,10 @@ #define XE2LPD_DE_CAP_SCALER_SINGLE 1 #define SKL_DSSM _MMIO(0x51004) -#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) -#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) -#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) -#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK REG_GENMASK(31, 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz 0 +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz REG_GENMASK(29, 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz REG_GENMASK(30, 29) /*GEN11 chicken */ #define _PIPEA_CHICKEN 0x70038 -- 2.45.2