Re: [PATCH v1 1/2] drm/i915/display: fix SKL_DSSM register masks
Jani Nikula <[email protected]> Tue, 28 Jul 2026 10:44:05 +0300
| Newsgroups | org.freedesktop.lists.intel-gfx,org.freedesktop.lists.intel-xe |
|---|---|
| Organization | Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland |
| Message-ID | <[email protected]> |
On Tue, 28 Jul 2026, Michał Grzelak <[email protected]> wrote: > Add indentation into SKL_DSSM reference clock macros. Replace bit shifts > with REG_GENMASK(). > > Signed-off-by: Michał Grzelak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 0f5018482497..0677ca2dde00 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -1779,10 +1779,10 @@ > #define XE2LPD_DE_CAP_SCALER_SINGLE 1 > > #define SKL_DSSM _MMIO(0x51004) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK REG_GENMASK(31, 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz 0 > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz REG_GENMASK(29, 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz REG_GENMASK(30, 29) Define _MASK with REG_GENMASK and values with REG_FIELD_PREP. The above is just plain wrong. > > /*GEN11 chicken */ > #define _PIPEA_CHICKEN 0x70038 -- Jani Nikula, Intel