[PATCH 2/2] drm/i915/display: Reconcile cdclk SW state with HW on DC-off exit
Arun R Murthy <[email protected]>
| Newsgroups | org.freedesktop.lists.intel-gfx,org.freedesktop.lists.intel-xe |
|---|---|
| Message-ID | <[email protected]> |
Add intel_cdclk_sync_hw_state() which adopts the HW-asserted cdclk into display->cdclk.hw and the committed cdclk_state (actual/logical) so that future atomic checks operate on a truthful baseline. Any pipe that needs more cdclk than HW is currently delivering will then naturally attach a cdclk_state via intel_cdclk_atomic_check() and raise cdclk through the normal modeset path. voltage_level cannot be reliably read back on all gens, so the SW value is preserved. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16595 Signed-off-by: Arun R Murthy <[email protected]> Tested-by: Polo-François Poli <[email protected]> --- drivers/gpu/drm/i915/display/intel_cdclk.h | 2 ++ drivers/gpu/drm/i915/display/intel_display_power_well.c | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index a60cbf745ee2638a092dbdce98b994b17d7009ef..ed78c855320ad4e92364989fd3f9248748a9de8a 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -69,6 +69,8 @@ int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state); void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk); void intel_cdclk_read_hw(struct intel_display *display); +void intel_cdclk_sync_hw_state(struct intel_display *display, + const struct intel_cdclk_config *hw_config); unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state); unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 02cb4d800e2389fc2a7d958ed78339a74f5c057e..11b8521d9d0c8b5381d3b90b5cbf24b97deacf65 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1105,6 +1105,7 @@ void gen9_disable_dc_states(struct intel_display *display) intel_cdclk_get_cdclk(display, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ + intel_cdclk_sync_hw_state(display, &cdclk_config); drm_WARN_ON(display->drm, intel_cdclk_clock_changed(&display->cdclk.hw, &cdclk_config)); -- 2.25.1