[PATCH 13/44] drm/i915/hdmi: Add function to prepare registers for FRL mode

Add intel_hdmi_prepare_for_frl_mode() to arm the FRL function and reset
the training pattern to the default LTP1 on all active lanes, before the
Link training sequence starts.

Signed-off-by: Ankit Nautiyal <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  2 +-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b0534fba4e5f..96542869740e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3501,3 +3501,25 @@ int intel_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector)
 
 	return max_lanes * rate_per_lane;
 }
+
+void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder trans = crtc_state->cpu_transcoder;
+	int num_lanes = crtc_state->frl.required_lanes;
+	u32 write_buf = 0;
+	int lane;
+
+	if (!crtc_state->frl.enable)
+		return;
+
+	intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, trans),
+		     TRANS_HDMI_FRL_TRAINING_COMPLETE,
+		     TRANS_HDMI_FRL_ENABLE);
+
+	/* Reset Training Pattern to default 0x1 */
+	for (lane = 0; lane < num_lanes; lane++)
+		write_buf |= TRANS_HDMI_FRL_LTP(0x1, lane);
+
+	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index c95ed37bcc0c..6283305b5274 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -63,7 +63,7 @@ int intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 				  int hdmi_max_slices, int hdmi_throughput);
 int intel_hdmi_dsc_get_slice_height(int vactive);
 bool intel_hdmi_is_frl(u32 clock);
-
+void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state);
 void hsw_write_infoframe(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state,
 			 unsigned int type,
-- 
2.50.1