RE: [PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout

> -----Original Message-----
> From: Jani Nikula <[email protected]>
> Sent: Friday, August 7, 2026 1:33 PM
> To: Manna, Animesh <[email protected]>; intel-
> [email protected]; [email protected]
> Cc: Manna, Animesh <[email protected]>; Dibin Moolakadan
> Subrahmanian <[email protected]>; Shankar,
> Uma <[email protected]>
> Subject: Re: [PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid
> disable timeout
> 
> On Fri, 07 Aug 2026, Animesh Manna <[email protected]> wrote:
> > CMTG is enabled in sync-to-port mode, so its running state
> > (CMTG_STATE) can only clear while the port is actively timing. In
> > hsw_crtc_disable() the CMTG was torn down at the very beginning of the
> > sequence, before the encoders were disabled. At that point PSR may
> > still be active on the eDP, leaving the port timing generator idle. As
> > a result, after clearing CMTG_ENABLE the wait for CMTG_STATE to clear
> never completes and triggers:
> >
> >   xe 0000:00:02.0: [drm] CMTG: A disable timeout
> >   WARNING: drivers/gpu/drm/i915/display/intel_cmtg.c:205
> > intel_cmtg_disable+0x331/0x3d0 [xe]
> >
> > This is intermittently seen with igt@kms_hdr@bpc-switch-suspend, which
> > repeatedly cycles the eDP in and out of PSR across suspend/resume.
> >
> > Move the CMTG disable to after intel_encoders_disable() (so PSR is
> > exited) but before intel_encoders_post_disable()/intel_dpll_disable(),
> > so the transcoder timing generator and port PLL are still active while
> > CMTG_STATE is polled. The ordering requirement of disabling CMTG
> > before the transcoder and port PLL are brought down is preserved.
> >
> > Cc: Dibin Moolakadan Subrahmanian
> > <[email protected]>
> > Cc: Uma Shankar <[email protected]>
> > Signed-off-by: Animesh Manna <[email protected]>
> 
> Fixes: ?
> Cc: stable ?

Sure, will add in next version.

Regards,
Animesh
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++----
> >  1 file changed, 14 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 829d7a411dcc..cc4d20fdda44 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1791,15 +1791,25 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> >  		intel_atomic_get_old_crtc_state(state, crtc);
> >  	struct intel_crtc *pipe_crtc;
> >
> > -	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
> > -		intel_cmtg_set_clk_select(old_crtc_state);
> > -		intel_cmtg_disable(old_crtc_state);
> > -	}
> >  	/*
> >  	 * FIXME collapse everything to one hook.
> >  	 * Need care with mst->ddi interactions.
> >  	 */
> >  	intel_encoders_disable(state, crtc);
> > +
> > +	/*
> > +	 * Disable CMTG after the encoders are disabled (so PSR is exited) but
> > +	 * before the transcoder timing generator and port PLL are torn down
> in
> > +	 * intel_encoders_post_disable()/intel_dpll_disable(). CMTG is
> synced to
> > +	 * the port, so its running state (CMTG_STATE) can only clear while
> the
> > +	 * port is actively timing. Doing this while PSR is still active leaves
> > +	 * the port idle and makes the CMTG_STATE clear wait time out.
> > +	 */
> > +	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
> > +		intel_cmtg_set_clk_select(old_crtc_state);
> > +		intel_cmtg_disable(old_crtc_state);
> > +	}
> > +
> >  	intel_encoders_post_disable(state, crtc);
> >
> >  	intel_dpll_disable(old_crtc_state);
> 
> --
> Jani Nikula, Intel