RE: [PATCH v2 2/8] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP

> Subject: [PATCH v2 2/8] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
> 
> The FRL bandwidth check considers only the PCON's max FRL rate, ignoring the
> HDMI2.1 sink's own max FRL rate. Cap the available bandwidth by the
> minimum of the two, similar to the TMDS case.
> 
> Move the check into a helper intel_dp_frl_bw_valid() so it can also be used in
> the compute_config phase in a subsequent change.
> 
> The DSC case, where both the PCON and HDMI sink support DSC, is left as a
> FIXME and handled later.
> 
> v2: Remove extra braces and re-format comment. (Suraj)
> 
> Signed-off-by: Ankit Nautiyal <[email protected]>

LGTM,
Reviewed-by: Suraj Kandpal <[email protected]>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 51 ++++++++++++++++---------
>  1 file changed, 34 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 437b9e7bb864..dd706f7de62d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -124,6 +124,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)  }
> 
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
> 
>  /* Is link rate UHBR and thus 128b/132b? */  bool intel_dp_is_uhbr(const struct
> intel_crtc_state *crtc_state) @@ -1179,30 +1180,46 @@ static int
> frl_required_bw(int clock, int bpc,  }
> 
>  static enum drm_mode_status
> -intel_dp_mode_valid_downstream(struct intel_connector *connector,
> -			       const struct drm_display_mode *mode,
> -			       int target_clock,
> -			       enum intel_output_format sink_format)
> +intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
> +		      int bpc, enum intel_output_format sink_format,
> +		      bool respect_downstream_limits)
>  {
> -	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +	int target_bw;
> +	int max_frl_bw;
> 
> -	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
> -	if (intel_dp->dfp.pcon_max_frl_bw) {
> -		int target_bw, max_frl_bw;
> +	if (!respect_downstream_limits)
> +		return MODE_OK;
> 
> -		/* Assume 8bpc for the FRL bandwidth check */
> -		target_bw = frl_required_bw(target_clock, 8, sink_format);
> +	target_bw = frl_required_bw(target_clock, bpc, sink_format);
> 
> -		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
> +	/* check for MAX FRL BW for both PCON and HDMI2.1 sink */
> +	max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
> +			 intel_dp_hdmi_sink_max_frl(intel_dp));
> 
> -		/* converting bw from Gbps to Kbps*/
> -		max_frl_bw = max_frl_bw * 1000000;
> +	/* converting bw from Gbps to Kbps*/
> +	max_frl_bw = max_frl_bw * 1000000;
> 
> -		if (target_bw > max_frl_bw)
> -			return MODE_CLOCK_HIGH;
> +	/* #FIXME check bandwidth with DSC if both PCON and HDMI sink
> support DSC */
> +	if (target_bw > max_frl_bw)
> +		return MODE_CLOCK_HIGH;
> 
> -		return MODE_OK;
> -	}
> +	return MODE_OK;
> +}
> +
> +static enum drm_mode_status
> +intel_dp_mode_valid_downstream(struct intel_connector *connector,
> +			       const struct drm_display_mode *mode,
> +			       int target_clock,
> +			       enum intel_output_format sink_format) {
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +
> +	/*
> +	 * If PCON supports FRL MODE, check FRL bandwidth constraints.
> +	 * Assume 8bpc for the HDMI2.1 FRL BW check
> +	 */
> +	if (intel_dp->dfp.pcon_max_frl_bw &&
> intel_dp_hdmi_sink_max_frl(intel_dp))
> +		return intel_dp_frl_bw_valid(intel_dp, target_clock, 8,
> sink_format,
> +true);
> 
>  	if (intel_dp->dfp.max_dotclock &&
>  	    target_clock > intel_dp->dfp.max_dotclock)
> --
> 2.50.1