[PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ

Currently we write the portclock as is into DDI_CLK_VALFREQ register.
Which is fine for HDMI TMDS and DP 8b/10b encoding but for DP
128b/132b and HDMI FRL port clock needs to be modified to the
appropriate symbol clock and then be written into this register.
H/w has not thrown a bug yet because this is a validation register
and has no functional impact on H/w.

Signed-off-by: Suraj Kandpal <[email protected]>

Suraj Kandpal (3):
  drm/i915/ddi: add helper to compute DDI clock frequency
  drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency
  drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency

 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  5 +++--
 drivers/gpu/drm/i915/display/intel_ddi.c     | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_ddi.h     |  1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c  |  6 ++++--
 4 files changed, 19 insertions(+), 4 deletions(-)

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2.34.1