RE: [PATCH] drm/i915/xe3p_lpd: Update CURSOR_BUF/WM masks
Gustavo Sousa <[email protected]>
| Newsgroups | org.freedesktop.lists.intel-gfx,org.freedesktop.lists.intel-xe |
|---|---|
| Message-ID | <[email protected]> |
"Bhadane, Dnyaneshwar" <[email protected]> writes: >> -----Original Message----- >> From: Intel-gfx <[email protected]> On Behalf Of >> Gustavo Sousa >> Sent: Saturday, July 25, 2026 12:05 AM >> To: [email protected]; [email protected] >> Cc: Kandpal, Suraj <[email protected]>; Sousa, Gustavo >> <[email protected]> >> Subject: [PATCH] drm/i915/xe3p_lpd: Update CURSOR_BUF/WM masks >> >> From: Suraj Kandpal <[email protected]> >> >> Xe3p onwards CURSOR_BUF/WM masks have been increased. Update them >> to reflect the following. >> >> Bspec: 69847, 69880 >> Signed-off-by: Suraj Kandpal <[email protected]> >> Signed-off-by: Gustavo Sousa <[email protected]> > > LGTM, > Reviewed-by: Dnyaneshwar Bhadane <[email protected]> Pushed to drm-intel-next. Thanks for the review! -- Gustavo Sousa > >> --- >> drivers/gpu/drm/i915/display/intel_cursor_regs.h | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h >> b/drivers/gpu/drm/i915/display/intel_cursor_regs.h >> index aaa66331063e..da2f9630ae2d 100644 >> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h >> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h >> @@ -81,7 +81,7 @@ >> #define CUR_WM_EN REG_BIT(31) >> #define CUR_WM_IGNORE_LINES REG_BIT(30) >> #define CUR_WM_LINES_MASK REG_GENMASK(26, >> 14) >> -#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, >> 0) >> +#define CUR_WM_BLOCKS_MASK REG_GENMASK(12, >> 0) >> >> #define _CUR_WM_SAGV_A 0x70158 >> #define _CUR_WM_SAGV_B 0x71158 >> @@ -98,10 +98,10 @@ >> #define _CUR_BUF_CFG_A 0x7017c >> #define _CUR_BUF_CFG_B 0x7117c >> #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, >> _CUR_BUF_CFG_B) >> -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ >> -#define CUR_BUF_END_MASK REG_GENMASK(27, 16) >> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3plpd+ 13 bits */ >> +#define CUR_BUF_END_MASK REG_GENMASK(28, 16) >> #define CUR_BUF_END(end) >> REG_FIELD_PREP(CUR_BUF_END_MASK, (end)) >> -#define CUR_BUF_START_MASK REG_GENMASK(11, 0) >> +#define CUR_BUF_START_MASK REG_GENMASK(12, 0) >> #define CUR_BUF_START(start) >> REG_FIELD_PREP(CUR_BUF_START_MASK, (start)) >> >> /* tgl+ */ >> >> --- >> base-commit: 8d8b015ca4cebab74621f83c223eacce22cc6f0e >> change-id: 20260724-xe3p_lpd-cursor-dbuf-increase-b8473ae029e0 >> >> Best regards, >> -- >> Gustavo Sousa <[email protected]>