[PATCH v4 3/3] drm/xe/guc_ads: use uncached mapping for UM queue BO
Jia Yao <[email protected]>
| Newsgroups | org.freedesktop.lists.intel-xe,org.kernel.vger.stable |
|---|---|
| Message-ID | <[email protected]> |
The HW unit that writes fault descriptors into the UM queue ring buffer
may not be coherent with the CPU cache. If a descriptor write is still
sitting in a GPU L3 cache line when GuC reads the slot, GuC sees the
stale (all-zero) content from DRAM and forwards an invalid descriptor to
the driver (Faulted Address = 0, ASID = 0).
Mark the UM queue BO as uncached (XE_BO_FLAG_NEEDS_UC) so that writes
bypass the cache and are immediately visible to GuC.
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: Gwan-gyeong Mun <[email protected]>
Cc: Matthew Auld <[email protected]>
Cc: [email protected]
Signed-off-by: Jia Yao <[email protected]>
---
drivers/gpu/drm/xe/xe_guc_ads.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 53636333fb45..76029575aa45 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -412,7 +412,8 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
XE_BO_FLAG_GGTT |
XE_BO_FLAG_GGTT_INVALIDATE |
- XE_BO_FLAG_PINNED_NORESTORE;
+ XE_BO_FLAG_PINNED_NORESTORE |
+ XE_BO_FLAG_NEEDS_UC;
bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
if (IS_ERR(bo))
--
2.43.0