[PATCH 0/2] drm/i915/flipq: Fix cursor left enabled after a pipe disable

IGT's kms_cursor_crc reproducibly triggers:

  cursor D assertion failure (expected off, current on)
  WARNING: .../intel_display.c:406 at assert_plane+0x11e/0x140 [xe]

from assert_planes_disabled() during a modeset pipe teardown, even
though the cursor plane is correctly targeted for disable and its
software state tracks it as disabled. The hardware register is never
rewritten because a stale flip queue entry from an earlier, unrelated
commit is discarded without invalidating the cursor's register
write-cache, so the disable update believes hardware already matches
and skips the write.

Patch 1 adds an explicit flip queue drain right before pipes have
their planes synchronously disabled, so a queued-but-not-yet-executed
update can no longer be left dangling past that point.

Patch 2 fixes the actual root cause: intel_flipq_reset(), which patch 1
(and pipe DMC firmware (re)load) calls to discard a flip queue's ring
buffer, did not invalidate the cursor's register cache, so a discarded
write could be silently "forgotten" while software still believed it
had taken effect. The cache is now invalidated whenever the queue is
reset, forcing the next update to always rewrite the real registers.

Mika Kahola (2):
  drm/i915/flipq: Drain the flip queue before disabling pipe planes
  drm/i915/flipq: Invalidate cursor register cache on flip queue reset

 drivers/gpu/drm/i915/display/intel_display.c |  2 ++
 drivers/gpu/drm/i915/display/intel_flipq.c   | 28 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_flipq.h   |  1 +
 3 files changed, 31 insertions(+)

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2.43.0