[PATCH 5/6] drm/xe/guc: add TDL gfx registers to capture list
Nareshkumar Gollakoti <[email protected]>
| Newsgroups | org.freedesktop.lists.intel-xe |
|---|---|
| Message-ID | <[email protected]> |
Add ROW_INSDONE_TDL_GFX and SS_LSC_HDC_IDLE_TDL_GFX register definitions and include them in the XeHPG extended GuC capture register list. This makes the TDL gfx state available in GuC error captures for debugging hang and fault scenarios. Signed-off-by: Nareshkumar Gollakoti <[email protected]> --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++ drivers/gpu/drm/xe/xe_guc_capture.c | 4 +++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 25014bccd3a6..8c55d766a5a6 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -572,6 +572,9 @@ #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) +#define ROW_INSDONE_TDL_GFX XE_REG_MCR(0xe580) +#define SS_LSC_HDC_IDLE_TDL_GFX XE_REG_MCR(0xe584) + #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index 368769857c9b..a6052da71787 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -376,7 +376,9 @@ static const struct __ext_steer_reg xehpg_extregs[] = { {"SC_INSTDONE", XEHPG_SC_INSTDONE}, {"SC_INSTDONE_EXTRA", XEHPG_SC_INSTDONE_EXTRA}, {"SC_INSTDONE_EXTRA2", XEHPG_SC_INSTDONE_EXTRA2}, - {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT} + {"INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT}, + {"ROW_INSDONE_TDL_GFX", ROW_INSDONE_TDL_GFX}, + {"SS_LSC_HDC_IDLE_TDL_GFX", SS_LSC_HDC_IDLE_TDL_GFX} }; static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, -- 2.43.0