Re: [PATCH] drm/xe/xe_gt_idle: Add CCS to the powergating info print
Matt Roper <[email protected]>
| Newsgroups | org.freedesktop.lists.intel-xe |
|---|---|
| Message-ID | <[email protected]> |
On Wed, Aug 19, 2026 at 01:04:58PM +0530, Balasubramani Vivekanandan wrote:
> While reading the main GT powergating info from debugfs, include both
> RCS and CCS engine masks.
>
> Fixes: 0914c1e45d3a1 ("drm/xe/xe_gt_idle: add debugfs entry for powergating info")
> Signed-off-by: Balasubramani Vivekanandan <[email protected]>
Yep, "render" domain is the power domain that also contains the compute
pipeline, EUs, etc.
Reviewed-by: Matt Roper <[email protected]>
and applied to drm-xe-next. Thanks for the patch!
Matt
> ---
> drivers/gpu/drm/xe/xe_gt_idle.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
> index 04b24e1c8b78e..7dc9873aef545 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
> @@ -248,7 +248,8 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
> pg_status = xe_mmio_read32(>->mmio, POWERGATE_DOMAIN_STATUS);
> }
>
> - if (gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK) {
> + if (gt->info.engine_mask &
> + (XE_HW_ENGINE_RCS_MASK | XE_HW_ENGINE_CCS_MASK)) {
> drm_printf(p, "Render Power Gating Enabled: %s\n",
> str_yes_no(pg_enabled & RENDER_POWERGATE_ENABLE));
>
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation