Re: [PATCH RFC] drm/nouveau: Use write-combined maps for coherent on Tegra

Am Samstag, dem 25.07.2026 um 18:28 -0500 schrieb Aaron Kling via B4
Relay:
> From: Faith Ekstrand <[email protected]>
>=20
> On Tegra devices, uncached maps traslate to device memory, causing
> unaligned accesses by userspace resulting in a SIGBUS. Instead, use
> write-combined maps to ensure proper access.
>=20
This is not only an issue on Tegra. All ARM64 platforms translate
uncached to device memory, which does not support unaligned access. So
the issue could happen in the same way when connecting a discrete GPU
to a ARM64 platform with PCIe support.

I would argue that there is no downside to always using write combined
memory for coherent buffers. You gain potentially faster writes while
the only issue is that writes may get delayed visibility at the device
side. However, I don't think anyone uses coherent buffers to modify the
content from the CPU side while the device is operating on the buffer.
For all regular use-case the memory barrier in FIRE_RING() will make
sure that the buffered writes are visible to the device before the
commands using the buffer are made visible to the device.

Regards,
Lucas

> Signed-off-by: Faith Ekstrand <[email protected]>
> Co-developed-by: Aaron Kling <[email protected]>
> Signed-off-by: Aaron Kling <[email protected]>
> ---
> This patch is marked RFC because there is not complete confidence that
> the change is correct. Without this change, nouveau can easily hit
> sigbus errors in Android UI rendering via nvk or running vulkan deqp
> tests on Tegra. Changing coherent maps to use write-combined stops the
> crashing, but it is unknown what the performance impact is, if any.
> ---
>  drivers/gpu/drm/nouveau/nouveau_sgdma.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>=20
> diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/no=
uveau/nouveau_sgdma.c
> index fa3b4ebf38a83..10f6ef1c541bd 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
> @@ -72,9 +72,12 @@ nouveau_sgdma_create_ttm(struct ttm_buffer_object *bo,=
 uint32_t page_flags)
>  	struct nouveau_sgdma_be *nvbe;
>  	enum ttm_caching caching;
> =20
> -	if (nvbo->force_coherent)
> -		caching =3D ttm_uncached;
> -	else if (drm->agp.bridge)
> +	if (nvbo->force_coherent) {
> +		if (drm->client.device.info.platform =3D=3D NV_DEVICE_INFO_V0_SOC)
> +			caching =3D ttm_write_combined;
> +		else
> +			caching =3D ttm_uncached;
> +	} else if (drm->agp.bridge)
>  		caching =3D ttm_write_combined;
>  	else
>  		caching =3D ttm_cached;
>=20
> ---
> base-commit: 1a1757b76427f6201bfe0bf1bea9f7574f332a93
> change-id: 20260725-tegra-coherent-wc-19941d1a5a60
>=20
> Best regards,