Re: [PATCH 1/6] clk: imx8mp: add 700 MHz rate entry for VIDEO_PLL1

On 6/2/26 6:09 AM, Johannes Schneider wrote:
> From: Thomas Haemmerle <[email protected]>
> 
> The LVDS serializer requires link_freq = pixel_clock × 7.  For a 25 MHz
> pixel clock the link frequency is 175 MHz.  VIDEO_PLL1 must be set to
> 700 MHz so the divider chain (VIDEO_PLL1 / 4 = 175 MHz) produces an
> exact match; without it clk_set_rate() rounds down to 650 MHz, yielding
> only 162.5 MHz and causing the LVDS transmitter to output ~743 pixels
> per line instead of 800 — visible as a black strip on the right edge.
> 
> PLL parameters: Fin=24 MHz, P=3, S=2, K=0 → 24 × 350 / (3 × 4) = 700 MHz.
> 
> Assisted-by: Claude:claude-sonnet-4-6
> Signed-of-by: Thomas Haemmerle <[email protected]>

Reviewed-by: Ahmad Fatoum <[email protected]>

> ---
>  drivers/clk/imx/clk-pll14xx.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
> index 6716a6f555..db7e744e87 100644
> --- a/drivers/clk/imx/clk-pll14xx.c
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -61,6 +61,7 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
>  };
>  
>  static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
> +	PLL_1443X_RATE(700000000U, 350, 3, 2, 0),
>  	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
>  	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
>  	PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
> 
> base-commit: 81fbe2e8d0d445032498a0bfecf9fd270f00985a

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