[PATCH v2 01/11] clk: imx8mp: add 700 MHz rate entry for VIDEO_PLL1
Johannes Schneider <[email protected]>
| Newsgroups | org.infradead.lists.barebox |
|---|---|
| Message-ID | <[email protected]> |
From: Thomas Haemmerle <[email protected]> LVDS link_freq = pixel_clock * 7. For a 25 MHz pixel clock that's 175 MHz, requiring VIDEO_PLL1 at 700 MHz so the /4 divider yields an exact match. Without the table entry, clk_set_rate() rounds down to 650 MHz (giving 162.5 MHz) and the LVDS transmitter outputs ~743 pixels per 800-pixel line. PLL parameters: Fin=24 MHz, P=3, S=2, K=0 -> 24 * 350 / (3 * 4) = 700 MHz. Reviewed-by: Ahmad Fatoum <[email protected]> Signed-off-by: Thomas Haemmerle <[email protected]> --- drivers/clk/imx/clk-pll14xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 6716a6f555..db7e744e87 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -61,6 +61,7 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { }; static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { + PLL_1443X_RATE(700000000U, 350, 3, 2, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(594000000U, 198, 2, 2, 0), PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), -- 2.43.0