[PATCH v2 02/11] clk: imx8mp: add 1039.5 MHz and 519.75 MHz rate entries for VIDEO_PLL1

The upstream arch/arm64/boot/dts/freescale/imx8mp.dtsi pins VIDEO_PLL1
to 1039.5 MHz (1080p60 LVDS link, 148.5 MHz * 7) via media_blk_ctrl's
assigned-clock-rates.  Without the table entry, that assignment fails
-EINVAL at media_blk_ctrl probe and the clock tree below LCDIF2 is
broken before lcdif2's own assigned-clock-rates can rebind it.

Add the 1039.5 MHz entry and the 519.75 MHz dual-link half-rate from
Linux's imx_pll1443x_tbl.  Parameters:
  Fout = 24 MHz * (m + k/65536) / (p * 2^s)
  1039.5 MHz: m=173, p=2, s=1, k=16384
   519.75 MHz: m=173, p=2, s=2, k=16384

Signed-off-by: Johannes Schneider <[email protected]>
---
 drivers/clk/imx/clk-pll14xx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index db7e744e87..8a773f19f8 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -61,9 +61,11 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
 };
 
 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
+	PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
 	PLL_1443X_RATE(700000000U, 350, 3, 2, 0),
 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
 	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
+	PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
 	PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
 	PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
 };
-- 
2.43.0