Re: [PATCH] usb: dwc2: skip polling for the soft reset clear bit and add after reset delay

On 2026-06-23 10:23, chalianis1 wrote:
> From: Chali Anis <[email protected]>
> 
> The RPi4 SoC do not deassert GRSTCTL_CSFTRST within the expected
> window but continue to operate correctly, causing probe to fail
> with ETIMEDOUT.

Does "within the expected window" imply that there is a bigger window in
which it is de-asserted?

> 
> Per the datasheet, GRSTCTL_CSFTRST is self-clearing but requires at least
> 3 PHY clocks after reset before any PHY domain access. Add a 1us delay to
> satisfy this requirement.

Which datasheet, the SoC datasheet or a DWC2 datasheet?

I'm just asking if there is a chance to not need a SoC check here.

Sascha

> 
> Signed-off-by: Chali Anis <[email protected]>
> ---
>  drivers/usb/dwc2/core.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
> index 60cc690fdbc0..6d4b7930da9e 100644
> --- a/drivers/usb/dwc2/core.c
> +++ b/drivers/usb/dwc2/core.c
> @@ -809,11 +809,16 @@ int dwc2_core_reset(struct dwc2 *dwc2)
>  	greset |= GRSTCTL_CSFTRST;
>  	dwc2_writel(dwc2, greset, GRSTCTL);
>  
> -	ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> -	if (ret) {
> -		dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
> +	/* Wait for at least 3 PHY Clocks */
> +	udelay(1);
> +
> +	if (!of_machine_is_compatible("brcm,bcm2711")) {
> +		ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> +		if (ret) {
> +			dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
>  				__func__);
> -		return ret;
> +			return ret;
> +		}
>  	}
>  
>  	if (wait_for_host_mode)
> 

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