[PATCH v2 11/11] mci: imx-esdhc: DMA in the i.MX8M PBL eMMC loader

The PBL eMMC loader was hardwired to PIO. Add an opt-in SDMA/ADMA2 path:
a per-loader transfer-mode choice (PIO default / SDMA / ADMA2), route the
imx8m and imx8mp/imx8mn loaders through shared helpers, and retry in PIO if
the DMA attempt fails so a misconfigured board still boots. The PBL has no
mci and runs before BL31, so host.sdhci.version is set by hand and the
ADMA2 descriptor table lives in a static buffer.

On the imx8mp loader the DMA mode is set up before the bootpart EXT_CSD
read so that read also goes through ADMA: a PIO transfer preceding the
first ADMA transfer wedges the uSDHC ADMA engine.

Measured on i.MX8MM (MMU on): load_bl33 241 ms (PIO) -> 28 ms (ADMA2).
SDMA and ADMA2 perform identically (bus-bound); SDMA needs no descriptor
table, so it is the simpler default for boards that just want the speedup.

Assisted-by: Claude Opus 4.8 (1M context)
Signed-off-by: Johannes Schneider <[email protected]>
---

Unlike v1 [1], this runs with the MMU on: the loader already enables the
MMU before the load (warm-cache PIO), and the SDMA/ADMA2 modes select
PBL_HAS_DMA so the transfer gets real dma_map/dma_sync cache maintenance
and stays coherent with the D-cache -- which is the memory-synchronization
the reviewer noted the PBL was missing [2].

[1] https://lists.infradead.org/pipermail/barebox/2026-June/056843.html
[2] https://lists.infradead.org/pipermail/barebox/2026-June/056842.html

Notes:
    v2:
    - Was v1 7/7. Now runs with the MMU on: the SDMA/ADMA2 modes select
      PBL_HAS_DMA so the transfer stays coherent with the D-cache, rather
      than relying on the MMU being off. Folds in the transfer-mode Kconfig.
    - Still retries in PIO if the DMA attempt fails.
    
    - SDMA/ADMA2 now depends on HAS_DMA && MMU so the select PBL_HAS_DMA does
      not bypass its own deps (Copilot).
    - imx8mp loader re-reads the boot partition after falling back to PIO, so
      a failed-DMA EXT_CSD read no longer picks the wrong load offset (Copilot).
    - __esdhc_send_cmd() transfers in PIO when DMA setup left dma==SDHCI_NO_DMA
      (e.g. ADMA table build failed) instead of driving a DMA transfer (Copilot).

 drivers/mci/Kconfig            | 27 ++++++++++
 drivers/mci/imx-esdhc-common.c | 21 ++++++--
 drivers/mci/imx-esdhc-pbl.c    | 91 +++++++++++++++++++++++++++++++---
 3 files changed, 128 insertions(+), 11 deletions(-)

diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index ebe771216f..d9dc241be9 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -296,6 +296,33 @@ config MCI_IMX_ESDHC_PBL
 	bool
 	select MCI_SDHCI
 
+choice
+	prompt "i.MX8M PBL eMMC loader transfer mode"
+	default MCI_IMX_ESDHC_PBL_PIO
+	depends on MCI_IMX_ESDHC_PBL
+	help
+	  How the i.MX8M PBL reads the next boot stage from eMMC. The MMU is
+	  enabled for the load either way (a warm D-cache makes even PIO fast);
+	  PIO needs no DMA plumbing and is the safe default. SDMA/ADMA2 are
+	  faster still and select PBL_HAS_DMA so their transfers stay coherent
+	  with the D-cache on; on failure the loader falls back to PIO so the
+	  board still boots.
+
+config MCI_IMX_ESDHC_PBL_PIO
+	bool "PIO"
+
+config MCI_IMX_ESDHC_PBL_SDMA
+	bool "SDMA"
+	depends on HAS_DMA && MMU
+	select PBL_HAS_DMA
+
+config MCI_IMX_ESDHC_PBL_ADMA2
+	bool "ADMA2"
+	depends on HAS_DMA && MMU
+	select PBL_HAS_DMA
+
+endchoice
+
 config MCI_ATMEL_PBL
 	bool
 	select MCI_ATMEL
diff --git a/drivers/mci/imx-esdhc-common.c b/drivers/mci/imx-esdhc-common.c
index a0c2dee32d..76b0ce3bff 100644
--- a/drivers/mci/imx-esdhc-common.c
+++ b/drivers/mci/imx-esdhc-common.c
@@ -295,9 +295,17 @@ void esdhc_populate_sdhci(struct fsl_esdhc_host *host)
 				      SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
 }
 
-static bool esdhc_use_pio_mode(void)
+static bool esdhc_use_pio_mode(struct fsl_esdhc_host *host)
 {
-	return IN_PBL || IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO);
+	/*
+	 * In the PBL default to PIO, unless a caller explicitly opted into
+	 * ADMA2 (SDHCI_USE_ADMA, descriptor table set up) or SDMA
+	 * (SDHCI_USE_SDMA).
+	 */
+	if (IN_PBL)
+		return !(host->sdhci.flags & (SDHCI_USE_ADMA | SDHCI_USE_SDMA));
+
+	return IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO);
 }
 
 static int esdhc_setup_data(struct fsl_esdhc_host *host, struct mci_data *data,
@@ -317,7 +325,7 @@ static int esdhc_setup_data(struct fsl_esdhc_host *host, struct mci_data *data,
 
 	host->sdhci.sdma_boundary = 0;
 
-	if (esdhc_use_pio_mode())
+	if (esdhc_use_pio_mode(host))
 		sdhci_setup_data_pio(&host->sdhci, data);
 	else
 		sdhci_setup_data_dma(&host->sdhci, data, dma);
@@ -411,7 +419,12 @@ int __esdhc_send_cmd(struct fsl_esdhc_host *host, struct mci_cmd *cmd,
 
 	/* Wait until all of the blocks are transferred */
 	if (data) {
-		if (esdhc_use_pio_mode())
+		/*
+		 * dma == SDHCI_NO_DMA means DMA setup failed (e.g. ADMA table
+		 * build); sdhci_setup_data_dma() has already programmed PIO, and
+		 * the command was issued without the DMA bit, so transfer in PIO.
+		 */
+		if (esdhc_use_pio_mode(host) || dma == SDHCI_NO_DMA)
 			ret = sdhci_transfer_data_pio(&host->sdhci, cmd, data);
 		else
 			ret = sdhci_transfer_data_dma(&host->sdhci, cmd, data, dma);
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 2402b9aeaf..7ea826fab5 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -33,6 +33,12 @@
 
 static u8 ext_csd[512] __aligned(64);
 
+#ifdef CONFIG_MCI_IMX_ESDHC_PBL_ADMA2
+/* ADMA2 descriptor table for the PBL eMMC loader (the PBL has no allocator). */
+static u8 esdhc_adma_table[SDHCI_DEFAULT_ADMA_DESCS * SDHCI_ADMA2_32_DESC_SZ]
+	__aligned(8);
+#endif
+
 static int esdhc_send_ext_csd(struct fsl_esdhc_host *host)
 {
 	struct mci_cmd cmd = {};
@@ -255,6 +261,51 @@ int imx7_esdhc_start_image(int instance)
  * Return: If image successfully loaded, returns 0.
  * A negative error code is returned when this function fails.
  */
+/*
+ * Configure the PBL eMMC loader's DMA mode (ADMA2 or SDMA per Kconfig). The
+ * PBL has no mci, so host->sdhci.version is set by hand because
+ * __sdhci_read_caps() cannot run.
+ */
+static void imx8m_esdhc_pbl_setup_dma(struct fsl_esdhc_host *host)
+{
+	if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PBL_SDMA)) {
+		host->sdhci.version = SDHCI_SPEC_300;
+		host->sdhci.flags |= SDHCI_USE_SDMA;
+	}
+
+#ifdef CONFIG_MCI_IMX_ESDHC_PBL_ADMA2
+	host->sdhci.version = SDHCI_SPEC_300;
+	host->sdhci.adma_table = esdhc_adma_table;
+	host->sdhci.adma_addr = virt_to_phys(esdhc_adma_table);
+	host->sdhci.desc_sz = SDHCI_ADMA2_32_DESC_SZ;
+	host->sdhci.adma_table_cnt = SDHCI_DEFAULT_ADMA_DESCS;
+	host->sdhci.adma_table_sz = sizeof(esdhc_adma_table);
+	host->sdhci.flags |= SDHCI_USE_ADMA;
+#endif
+}
+
+static int imx8m_esdhc_load_image_dma(struct fsl_esdhc_host *host,
+				      struct esdhc_soc_data *data, int instance,
+				      void *bl33, u32 offset, u32 ivt_offset)
+{
+	int ret;
+
+	ret = esdhc_load_image(host, MX8M_DDR_CSD1_BASE_ADDR,
+			       (ptrdiff_t)bl33, offset, ivt_offset, false);
+	if (!ret)
+		return 0;
+
+	/* Fall back to PIO so a failed DMA attempt still boots. */
+	if (host->sdhci.flags & (SDHCI_USE_ADMA | SDHCI_USE_SDMA)) {
+		host->sdhci.flags &= ~(SDHCI_USE_ADMA | SDHCI_USE_SDMA);
+		imx8m_esdhc_init(host, data, instance);
+		ret = esdhc_load_image(host, MX8M_DDR_CSD1_BASE_ADDR,
+				       (ptrdiff_t)bl33, offset, ivt_offset, false);
+	}
+
+	return ret;
+}
+
 int imx8m_esdhc_load_image(int instance, void *bl33)
 {
 	struct esdhc_soc_data data;
@@ -265,9 +316,10 @@ int imx8m_esdhc_load_image(int instance, void *bl33)
 	if (ret)
 		return ret;
 
-	return esdhc_load_image(&host, MX8M_DDR_CSD1_BASE_ADDR,
-				(ptrdiff_t)bl33, SZ_32K, SZ_1K,
-				false);
+	imx8m_esdhc_pbl_setup_dma(&host);
+
+	return imx8m_esdhc_load_image_dma(&host, &data, instance, bl33,
+					  SZ_32K, SZ_1K);
 }
 
 /**
@@ -283,21 +335,46 @@ int imx8m_esdhc_load_image(int instance, void *bl33)
  * Return: If image successfully loaded, returns 0.
  * A negative error code is returned when this function fails.
  */
+static int imx8mp_esdhc_try_load(struct fsl_esdhc_host *host, void *bl33)
+{
+	u32 offset = esdhc_bootpart_active(host) ? 0 : SZ_32K;
+
+	return esdhc_load_image(host, MX8M_DDR_CSD1_BASE_ADDR,
+				(ptrdiff_t)bl33, offset, 0, false);
+}
+
 int imx8mp_esdhc_load_image(int instance, void *bl33)
 {
 	struct esdhc_soc_data data;
 	struct fsl_esdhc_host host = { 0 };
-	u32 offset;
 	int ret;
 
 	ret = imx8m_esdhc_init(&host, &data, instance);
 	if (ret)
 		return ret;
 
-	offset = esdhc_bootpart_active(&host)? 0 : SZ_32K;
+	/*
+	 * Set up DMA first so the EXT_CSD read below also goes through ADMA --
+	 * a PIO transfer before the first ADMA transfer wedges the 8MP uSDHC.
+	 */
+	imx8m_esdhc_pbl_setup_dma(&host);
 
-	return esdhc_load_image(&host, MX8M_DDR_CSD1_BASE_ADDR,
-				(ptrdiff_t)bl33, offset, 0, false);
+	ret = imx8mp_esdhc_try_load(&host, bl33);
+	if (!ret)
+		return 0;
+
+	/*
+	 * Fall back to PIO so a failed DMA attempt still boots. Re-read the
+	 * boot partition in PIO too, so the load offset is chosen with the same
+	 * transfer mode that does the load.
+	 */
+	if (host.sdhci.flags & (SDHCI_USE_ADMA | SDHCI_USE_SDMA)) {
+		host.sdhci.flags &= ~(SDHCI_USE_ADMA | SDHCI_USE_SDMA);
+		imx8m_esdhc_init(&host, &data, instance);
+		ret = imx8mp_esdhc_try_load(&host, bl33);
+	}
+
+	return ret;
 }
 
 int imx8mn_esdhc_load_image(int instance, void *bl33)
-- 
2.43.0