Re: QNS: ARM64: Cache coherency while doing Kexec for KHO

+ Added more folks to the lists

Tarun Sahu <[email protected]> writes:

> Hi,
>
> I have a question regarding cache maintenance for Kernel Handover (KHO)
> preserved memory across kexec reboots on arm64.
>
> During kexec, all other CPUs gets hot-unplugged where they flush all
> of their caches so there will be no issues with any KHO data preserved
> having caches on these CPUs.
>
> But CPU0 still has not been flushed its D-cache (Is this correct?) and
> it will only do flushing for specific area by kexec_segment_flush().
>
> So for KHO preserved memory, if its caches still marked dirty on CPU0
> they will not be flushed?
>
> Is my understanding correct? or AM I missing something?
> Also if this true, This will be a problem?
>
> PS: Pardon my less knowledge on ARM64 cache coherency.
>
> ~Tarun