Re: [PATCH v10 0/3] RISC-V: KVM: Validate SBI STA shmem alignment

Hello:

This series was applied to riscv/linux.git (fixes)
by Anup Patel <[email protected]>:

On Tue,  3 Mar 2026 01:08:56 +0000 you wrote:
> This series fixes a missing validation in the RISC-V KVM SBI
> steal-time accounting (STA) register handling.
> 
> Patch 1 validates the configured SBI STA shared memory GPA at
> KVM_SET_ONE_REG, enforcing the 64-byte alignment requirement
> defined by the SBI specification or allowing INVALID_GPA to explicitly
> disable steal-time accounting. This prevents invalid userspace state
> from reaching runtime code paths and avoids WARN_ON() triggers during
> KVM_RUN.
> 
> [...]

Here is the summary with links:
  - [v10,1/3] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg()
    https://git.kernel.org/riscv/c/fa9681ed5c6a
  - [v10,2/3] KVM: selftests: Refactor UAPI tests into dedicated function
    (no matching commit)
  - [v10,3/3] RISC-V: KVM: selftests: Add RISC-V SBI STA shmem alignment tests
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



-- 
kvm-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/kvm-riscv