Re: Re: [RFC PATCH 00/11] iommu/riscv: Add hardware dirty tracking for second-stage domains
| Newsgroups | org.infradead.lists.kvm-riscv,dev.linux.lists.iommu,org.infradead.lists.linux-riscv,org.kernel.vger.kvm,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
>> From: Fangyu Yu <[email protected]> >> >> The RISC-V IOMMU architecture defines an AMO_HWAD capability (Hardware >> Access/Dirty update) that allows the IOMMU to atomically set the A/D bits >> in second-stage PTEs on DMA access. When DC.tc.GADE is asserted, the IOMMU >> autonomously sets D on the first write to a page mapped by an iohgatp >> domain. This series wires that capability up to the iommufd dirty-tracking >> interface (IOMMU_HWPT_SET_DIRTY_TRACKING / IOMMU_HWPT_GET_DIRTY_BITMAP) and >> reports IOMMU_CAP_DIRTY_TRACKING. >> >> Design notes >> ------------ >> >> * The feature is scoped to second-stage (iohgatp) domains only; these are >> the domains created for KVM / VFIO device pass-through when userspace >> allocates an HWPT with IOMMU_HWPT_ALLOC_NEST_PARENT or >> IOMMU_HWPT_ALLOC_DIRTY_TRACKING. First-stage (iosatp) domains are not >> touched by this series. >> >> * The page-table side plugs into the existing generic_pt dirty hook >> framework (amdv1 / vtdss style). RISC-V adds the three required PTE >> ops – is_write_dirty / make_write_clean / make_write_dirty. >> >> Testing >> ------- >> >> * Test on QEMU RISC-V, a virtio-net and an e1000e device was passed through >> to an L2 guest via vfio-pci + iommufd. >> >> * generic_pt KUnit: the existing test_dirty case now runs and passes for >> the RISC-V 64-bit format. >> >> Follow-up work >> -------------- >> * Build a dedicated end-to-end test case that drives the full flow >> (HWPT_ALLOC with DIRTY_TRACKING -> attach -> IOAS_MAP -> generate real >> DMA -> SET_DIRTY_TRACKING -> GET_DIRTY_BITMAP -> verify bitmap against >> expected IOVA footprint) so that the behaviour can be regression-tested >> beyond the KUnit PTE-level coverage. >> >> * If possible, rebase and retest on top of the updated "iommu irqbypass" >> patchset. > >Thanks for this series! I was starting to go down a similar road myself >in order to limit irqbypass to IOMMU_HWPT_ALLOC_NEST_PARENT domains since >I wasn't happy with other approaches, e.g. continuing to use s-stage, but >activating g-stage too with identity mappings since the MSI table can't be >activated otherwise. Or, simply using g-stage instead of s-stage in order >to get the MSI table enabled. In the end, I think the best is to require >nested for irqbypass and this series will provide a good base for that. > >I'll rebase irqbypass on this series and test it out. > Thanks for the feedback. Jason has provided some helpful suggestions on this series, and I am in the process of updating it. I expect to send out a new version in the coming days. Fangyu >Thanks, >drew -- kvm-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/kvm-riscv