Re: [PATCH v2 01/16] riscv: Introduce instruction table generation

2026-06-21T21:01:19-07:00, Charlie Jenkins via B4 Relay <[email protected]>:
> From: Charlie Jenkins <[email protected]>
>
> Eliminate the need to hand-write riscv instructions by using a shell
> script to autogenerate a header from an instruction table. This is modeled
> after the syscall table infrastructure.
>
> The table is generated externally by riscv-unified-db [1], but is
> in a simple format to make it possible to use other tools or modify
> manually.
>
> [1] https://github.com/riscv-software-src/riscv-unified-db
>
> Signed-off-by: Charlie Jenkins <[email protected]>
>
> ---
> diff --git a/arch/riscv/tools/insn.tbl b/arch/riscv/tools/insn.tbl
> @@ -0,0 +1,1392 @@
> +# SPDX-License-Identifier: BSD-3-Clause-Clear
> +#
> +# GENERATED WITH https://github.com/riscv-software-src/riscv-unified-db
> +# "./bin/generate inst-table -o test_table.txt"

I checked out the repo, ran the command, and got a different table:

> +andn common 0100000<25|111<12|0110011<0 xs2=24-20 xs1=19-15 xd=11-7
   andn common 0100000<31|111<14|0110011<7 xs2=24-20 xs1=19-15 xd=11-7

I assume there were some recent changes in the output format...

I think it would be nice to use their latest format and also note the
UDB commit that was used, so it's easier to reproduce our file.
Hopefully there won't be breaking changes too often. :)

Thanks.

---
Sashiko seems to have noticed a plenty of other issues, so I didn't
review more...

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