Re: [PATCH 3/3] KVM: selftests: Enable pre_fault_memory_test for RISC-V
Sean Christopherson <[email protected]>
| Newsgroups | org.infradead.lists.kvm-riscv,org.infradead.lists.linux-riscv,org.kernel.vger.kvm,org.kernel.vger.linux-kernel,org.kernel.vger.linux-kselftest |
|---|---|
| Message-ID | <[email protected]> |
On Tue, Aug 11, 2026, Jinyu Tang wrote: > RISC-V now supports KVM_PRE_FAULT_MEMORY, so include the generic > pre_fault_memory_test in the RISC-V KVM selftest build. > > The test uses PAGE_SIZE from the architecture processor header. Define > the normal 4K RISC-V selftest page size so the generic test can build > for RISC-V. > > RISC-V selects VM_MODE_DEFAULT at runtime. Initialize the supported > guest modes before creating the VM so the generic test can run on > RISC-V hosts where the default mode is discovered from KVM > capabilities. > > Signed-off-by: Jinyu Tang <[email protected]> > --- ... > diff --git a/tools/testing/selftests/kvm/pre_fault_memory_test.c b/tools/testing/selftests/kvm/pre_fault_memory_test.c > index a0fcae3cb7a8..6eebf0524673 100644 > --- a/tools/testing/selftests/kvm/pre_fault_memory_test.c > +++ b/tools/testing/selftests/kvm/pre_fault_memory_test.c > @@ -8,6 +8,7 @@ > #include <linux/sizes.h> > > #include <test_util.h> > +#include <guest_modes.h> > #include <kvm_util.h> > #include <processor.h> > #include <pthread.h> > @@ -219,6 +220,8 @@ static void test_pre_fault_memory(unsigned long vm_type, bool private) > > int main(int argc, char *argv[]) > { > + guest_modes_append_default(); Can we do this for all selftests in kvm_selftest_init()? Or perhaps even better, handle it in kvm_selftest_arch_init() to avoid the gnarly #ifdefs? Unless there's a meaningful downside to configuring the supported and default modes, I don't see any reason to force tests to manually do this work. > + > TEST_REQUIRE(kvm_check_cap(KVM_CAP_PRE_FAULT_MEMORY)); > > test_pre_fault_memory(0, false); > -- > 2.43.0 > -- kvm-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/kvm-riscv