Re: [PATCH 08/21] dt-bindings: mfd: x-powers: add AC200
Chen-Yu Tsai <[email protected]> Tue, 4 Aug 2026 00:51:57 +0800
| Newsgroups | org.infradead.lists.linux-arm-kernel,dev.linux.lists.linux-sunxi,dev.linux.lists.mfd,org.infradead.lists.linux-rockchip,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.netdev |
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| Message-ID | <CAGb2v67Wo+WG47jF_vBUOwv0Vw1SDygXMdBgpsy3R1AQ_LLfHw@mail.gmail.com> |
On Tue, Aug 4, 2026 at 12:45 AM James Hilliard <[email protected]> wrote: > > On Mon, Aug 3, 2026 at 7:18 AM Andrew Lunn <[email protected]> wrote: > > > > > + ethernet-phy-control { > > > + compatible = "x-powers,ac200-ephy-ctl"; > > > + nvmem-cells = <&ephy_calibration>; > > > + nvmem-cell-names = "calibration"; > > > + phy-mode = "rmii"; > > > + }; > > > > What do you mean by an ethernet PHY control? > > > > I assume this is not an actual Ethernet PHY, but some control logic > > around it? Where is the ethernet PHY itself? > > Correct, this is not the Ethernet PHY itself. It is the package-specific > sideband control block that must be configured before the normal Clause 22 > PHY registers become usable. For AC200, this control block is accessed > through the parent AC200 I2C regmap. For AC300, the equivalent control block > is accessed through a separate non-PHY Clause 22 address. Basically, all the PHY behavior that is normally configured using strapping pins on a discrete PHY is done over this I2C channel. > The actual Ethernet PHY is a separate device on the MAC's MDIO bus. The > shared PHY driver for that device is added in patch 16: > > https://lore.kernel.org/linux-sunxi/[email protected]/ > > The later board DTS patches instantiate it as an ethernet-phy node beneath > the MAC's MDIO bus and reference the appropriate sideband control provider. > > > > > Andrew