Re: [PATCH v3 8/9] arm64: dts: st: Add USB nodes on stm32mp231

On 8/22/26 09:46, Marek Vasut wrote:
> Add USB controller and PHY nodes to stm32mp231 DT.
> This includes two USB 2.0 FEMTO PHYs, USB 2.0 host
> controller and DWC3 DRD controller nodes.
> 
> Co-developed-by: Alexandre Torgue <[email protected]>
> Signed-off-by: Alexandre Torgue <[email protected]>
> Co-developed-by: Francois Choleau <[email protected]>
> Signed-off-by: Francois Choleau <[email protected]>
> Signed-off-by: Marek Vasut <[email protected]>
> ---
> Cc: Alexandre Torgue <[email protected]>
> Cc: Christian Bruel <[email protected]>
> Cc: Conor Dooley <[email protected]>
> Cc: Fabrice Gasnier <[email protected]>
> Cc: Greg Kroah-Hartman <[email protected]>
> Cc: Krzysztof Kozlowski <[email protected]>
> Cc: Maxime Coquelin <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: Pankaj Dev <[email protected]>
> Cc: Rahul Kumar <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Rosen Penev <[email protected]>
> Cc: Thinh Nguyen <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> V2: - Fix up Sob/Cdb lines
>     - Move PHY into syscfg subnode
>     - Turn st,stm32mp23-syscfg into simple-mfd
>     - Use clock-cells = <1> to discern OSC and future PLL clock from the PHY
> V3: - Drop combophy which is not present on MP23
>     - Describe OHCI clock as the CMN clock
> ---
>  arch/arm64/boot/dts/st/stm32mp231.dtsi | 67 +++++++++++++++++++++++++-
>  1 file changed, 66 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
> index 4505fc0e3b537..314a514f31024 100644
> --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
> @@ -7,6 +7,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
>  #include <dt-bindings/reset/st,stm32mp25-rcc.h>
> +#include <dt-bindings/phy/phy.h>
>  
>  / {
>  	#address-cells = <2>;
> @@ -862,6 +863,48 @@ stmmac_axi_config_1: stmmac-axi-config {
>  					snps,wr_osr_lmt = <0x7>;
>  				};
>  			};
> +
> +			usbh_ohci: usb@482e0000 {
> +				compatible = "generic-ohci";
> +				reg = <0x482e0000 0x1000>;
> +				access-controllers = <&rifsc 63>;
> +				clocks = <&usb2_phy1 1>, <&rcc CK_BUS_USB2OHCI>;
> +				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +				phys = <&usb2_phy1>;
> +				phy-names = "usb";
> +				resets = <&rcc USBH_R>;
> +				status = "disabled";
> +			};
> +
> +			usbh_ehci: usb@482f0000 {
> +				compatible = "generic-ehci";
> +				reg = <0x482f0000 0x1000>;
> +				access-controllers = <&rifsc 63>;
> +				clocks = <&usb2_phy1 0>, <&rcc CK_BUS_USB2EHCI>;
> +				companion = <&usbh_ohci>;
> +				interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> +				phys = <&usb2_phy1>;
> +				phy-names = "usb";
> +				resets = <&rcc USBH_R>;
> +				status = "disabled";
> +			};
> +
> +			usb3dr: usb@48300000 {
> +				compatible = "st,stm32mp25-dwc3";
> +				reg = <0x48300000 0x100000>;
> +				access-controllers = <&rifsc 66>;
> +				clocks = <&rcc CK_KER_USB2PHY2>,
> +					 <&rcc CK_BUS_USB3DR>,
> +					 <&rcc CK_KER_USB2PHY2>;
> +				clock-names = "ref", "bus_early", "suspend";
> +				interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> +				maximum-speed = "high-speed";
> +				phys = <&usb2_phy2>;
> +				phy-names = "usb2-phy";
> +				resets = <&rcc USB3DR_R>;
> +				st,syscfg = <&syscfg 0x4800>;
> +				status = "disabled";
> +			};
>  		};
>  
>  		bsec: efuse@44000000 {
> @@ -1062,9 +1105,31 @@ exti1: interrupt-controller@44220000 {
>  		};
>  
>  		syscfg: syscon@44230000 {
> -			compatible = "st,stm32mp23-syscfg", "syscon";
> +			compatible = "st,stm32mp23-syscfg", "syscon", "simple-mfd";
>  			reg = <0x44230000 0x10000>;
>  			#clock-cells = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			usb2_phy1: phy@2400 {
> +				compatible = "st,stm32mp25-usb2phy1";
> +				reg = <0x2400 0x24>;

Hello Marek,

The size 0x24, covers the PHY control, trimming and vbus control logic
for PHY1 (USBH). So this allows to later extend the driver for that, right ?

> +				#phy-cells = <0>;
> +				#clock-cells = <1>;
> +				clocks = <&rcc CK_KER_USB2PHY1>;
> +				resets = <&rcc USB2PHY1_R>;
> +				status = "disabled";
> +			};
> +
> +			usb2_phy2: phy@2800 {
> +				compatible = "st,stm32mp25-usb2phy2";
> +				reg = <0x2800 0xc>;

Then here, I guess the size should cover also trimming regs ? e.g. 0x10 ?
				reg = <0x2800 0x10>;

Thanks & BR,
Fabrice

> +				#phy-cells = <0>;
> +				#clock-cells = <1>;
> +				clocks = <&rcc CK_KER_USB2PHY2EN>;
> +				resets = <&rcc USB2PHY2_R>;
> +				status = "disabled";
> +			};
>  		};
>  
>  		pinctrl: pinctrl@44240000 {