Re: [PATCH v2 3/3] arm64: dts: lx2160a: fix the iic5 spi3 pinmux offset and value

Am 24.08.26 um 15:12 schrieb Vincent Jardin via B4 Relay:

> From: Vincent Jardin <[email protected]>
>
> The iic5-spi3-pins node has both of its first two cells wrong.
>
> The offset selects the register within the node's reg range, where:
>   0x0 is RCWSR12,
>   0x4 is RCWSR13,
>   0x8 is RCWSR14.
>
> An offset of 0x3 is not one of them and is not even aligned for the
> declared 32 bit register width. It is the only node in this pinmux that
> does not use 0x0, 0x4 neither 0x8.
>
> The value is wrong too:
>   IIC5_PMUX is RCWSR12[11:9] and it encodes 0b000 for IIC5,
>   0b001 for GPIO_1[25:24],
>   0b010 for SDHC1_CLK_SYNC_OUT/IN,
>   0b011 for {IIC5_SCL,IIC5_SDA} = {SPI3_SOUT,SPI3_SIN}.
>
> This node selects the last of those, so it needs 0x3, not the 0x2, which
> is the value of the neighbouring sdhc1 clock sync node it was copied
> from.
>
> Fixes: 284ad7064aaa ("arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word")
> Signed-off-by: Vincent Jardin <[email protected]>
> ---
>  arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
> index fae705dd07669..bf5d9b671d858 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
> @@ -1602,7 +1602,7 @@ esdhc0_clksync_pins: iic5-sdhc-clk-pins {
>  			};
>  
>  			dspi2_miso_mosi_pins: iic5-spi3-pins {
> -				pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>;
> +				pinctrl-single,bits = <0x0 (0x3 << 9) (0x7 << 9)>;
>  			};
>  
>  			i2c5_pins: iic6-i2c-pins {
>
Reviewed-by: Josua Mayer <[email protected]>

Thanks for checking all these!