Re: [PATCH v5 05/17] i3c: renesas: Reset the controller on resume

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Hardware reset lines are deasserted before controller clocks are enabled during system resume.
--

--- Patch [5]: [PATCH v5 05/17] i3c: renesas: Reset the controller on resume ---
commit 9230535f3beec14a9429fad84d54b26dbaff5182
Author: Claudiu Beznea <[email protected]>

i3c: renesas: Reset the controller on resume

This commit updates the resume handler to reset the controller after enabling
the clocks to match the probe sequence. It also switches renesas_i3c_reset()
to use read_poll_timeout_atomic() since the resume callback runs in the noirq
phase.

> diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
> index 517ac2df9bd40..6590da962592a 100644
> --- a/drivers/i3c/master/renesas-i3c.c
> +++ b/drivers/i3c/master/renesas-i3c.c
[ ... ]
> @@ -1483,6 +1483,10 @@ static int renesas_i3c_resume_noirq(struct device *dev)
>  	if (ret)
>  		goto err_presetn;
>  
> +	ret = renesas_i3c_reset(i3c);
> +	if (ret)
> +		goto err_clks_disable;
> +

[Severity: High]
This isn't a bug introduced by this patch, but does the sequence in
renesas_i3c_resume_noirq() correctly handle hardware constraints?

Looking at the code just above this hunk, the resets are deasserted
before the clocks are enabled:

	ret = reset_control_deassert(i3c->tresetn);
	if (ret)
		return ret;

	ret = reset_control_deassert(i3c->presetn);
	if (ret)
		goto err_tresetn;

	ret = clk_bulk_enable(i3c->num_clks, i3c->clks);

Deasserting peripheral resets while its clocks are disabled can cause the
hardware to remain stuck in reset or enter an undefined, non-functional
state when the clocks are subsequently enabled. Could this leave the I3C
master unresponsive after resume?

>  	/* Re-store I3C registers value. */
>  	renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR);
>  	renesas_writel(i3c->regs, EXTBR, i3c->extbr);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=5

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