[PATCH v3 05/18] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186
Louis-Alexis Eyraud <[email protected]>
| Newsgroups | org.infradead.lists.linux-mediatek,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.netdev |
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| Message-ID | <20260720-mt8189-clocks-system-base-v3-5-8e6d99ab3ad2@collabora.com> |
Regroup the MT8188 clock and system clock dt-bindings into MT8186 ones to ease maintainability and have common files for several currently supported SoC or new future ones, that have the same kind of clock controller design. Acked-by: Conor Dooley <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Louis-Alexis Eyraud <[email protected]> --- .../bindings/clock/mediatek,mt8186-clock.yaml | 50 +++++++++++- .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 6 +- .../bindings/clock/mediatek,mt8188-clock.yaml | 93 ---------------------- .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 -------------- 4 files changed, 54 insertions(+), 153 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml index 756b937bb7c4..0bc2da60a601 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek Functional Clock Controller for MT8186 +title: MediaTek Functional Clock Controller for Mediatek SoCs maintainers: - Chun-Jie Chen <[email protected]> @@ -35,6 +35,29 @@ properties: - mediatek,mt8186-vdecsys - mediatek,mt8186-vencsys - mediatek,mt8186-wpesys + - mediatek,mt8188-adsp-audio26m + - mediatek,mt8188-camsys + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-ccusys + - mediatek,mt8188-imgsys + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-imp-iic-wrap-c + - mediatek,mt8188-imp-iic-wrap-en + - mediatek,mt8188-imp-iic-wrap-w + - mediatek,mt8188-ipesys + - mediatek,mt8188-mfgcfg + - mediatek,mt8188-vdecsys + - mediatek,mt8188-vdecsys-soc + - mediatek,mt8188-vencsys + - mediatek,mt8188-wpesys + - mediatek,mt8188-wpesys-vpp0 reg: maxItems: 1 @@ -42,11 +65,36 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg - '#clock-cells' +allOf: + - if: + properties: + compatible: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + then: + required: + - '#reset-cells' + else: + properties: + '#reset-cells': false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml index 6733dafbde16..199eac2034f2 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek System Clock Controller for MT8186 +title: MediaTek System Clock Controller for Mediatek SoCs maintainers: - Chun-Jie Chen <[email protected]> @@ -31,6 +31,10 @@ properties: - mediatek,mt8186-infracfg_ao - mediatek,mt8186-mcusys - mediatek,mt8186-topckgen + - mediatek,mt8188-apmixedsys + - mediatek,mt8188-infracfg-ao + - mediatek,mt8188-pericfg-ao + - mediatek,mt8188-topckgen - const: syscon reg: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml deleted file mode 100644 index 5403242545ab..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ /dev/null @@ -1,93 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek Functional Clock Controller for MT8188 - -maintainers: - - Garmin Chang <[email protected]> - -description: | - The clock architecture in MediaTek like below - PLLs --> - dividers --> - muxes - --> - clock gate - - The devices provide clock gate control in different IP blocks. - -properties: - compatible: - enum: - - mediatek,mt8188-adsp-audio26m - - mediatek,mt8188-camsys - - mediatek,mt8188-camsys-rawa - - mediatek,mt8188-camsys-rawb - - mediatek,mt8188-camsys-yuva - - mediatek,mt8188-camsys-yuvb - - mediatek,mt8188-ccusys - - mediatek,mt8188-imgsys - - mediatek,mt8188-imgsys-wpe1 - - mediatek,mt8188-imgsys-wpe2 - - mediatek,mt8188-imgsys-wpe3 - - mediatek,mt8188-imgsys1-dip-nr - - mediatek,mt8188-imgsys1-dip-top - - mediatek,mt8188-imp-iic-wrap-c - - mediatek,mt8188-imp-iic-wrap-en - - mediatek,mt8188-imp-iic-wrap-w - - mediatek,mt8188-ipesys - - mediatek,mt8188-mfgcfg - - mediatek,mt8188-vdecsys - - mediatek,mt8188-vdecsys-soc - - mediatek,mt8188-vencsys - - mediatek,mt8188-wpesys - - mediatek,mt8188-wpesys-vpp0 - - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -allOf: - - if: - properties: - compatible: - contains: - enum: - - mediatek,mt8188-camsys-rawa - - mediatek,mt8188-camsys-rawb - - mediatek,mt8188-camsys-yuva - - mediatek,mt8188-camsys-yuvb - - mediatek,mt8188-imgsys-wpe1 - - mediatek,mt8188-imgsys-wpe2 - - mediatek,mt8188-imgsys-wpe3 - - mediatek,mt8188-imgsys1-dip-nr - - mediatek,mt8188-imgsys1-dip-top - - mediatek,mt8188-ipesys - - then: - required: - - '#reset-cells' - -additionalProperties: false - -examples: - - | - clock-controller@11283000 { - compatible = "mediatek,mt8188-imp-iic-wrap-c"; - reg = <0x11283000 0x1000>; - #clock-cells = <1>; - }; - diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml deleted file mode 100644 index db13d51a4903..000000000000 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml +++ /dev/null @@ -1,58 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek System Clock Controller for MT8188 - -maintainers: - - Garmin Chang <[email protected]> - -description: | - The clock architecture in MediaTek like below - PLLs --> - dividers --> - muxes - --> - clock gate - - The apmixedsys provides most of PLLs which generated from SoC 26m. - The topckgen provides dividers and muxes which provide the clock source to other IP blocks. - The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. - The mcusys provides mux control to select the clock source in AP MCU. - The device nodes also provide the system control capacity for configuration. - -properties: - compatible: - items: - - enum: - - mediatek,mt8188-apmixedsys - - mediatek,mt8188-infracfg-ao - - mediatek,mt8188-pericfg-ao - - mediatek,mt8188-topckgen - - const: syscon - - reg: - maxItems: 1 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - -required: - - compatible - - reg - - '#clock-cells' - -additionalProperties: false - -examples: - - | - clock-controller@10000000 { - compatible = "mediatek,mt8188-topckgen", "syscon"; - reg = <0x10000000 0x1000>; - #clock-cells = <1>; - }; -- 2.55.0