Re: [PATCH v1] pmdomain: mediatek: Fix MT8183 hang on boot
Ulf Hansson <[email protected]>
| Newsgroups | org.infradead.lists.linux-mediatek,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pm |
|---|---|
| Message-ID | <CAPx+jO-1_ZpYcnPtoYxRn5vv34tiP7TXnjKZ3SaWkEzdeTfXpA@mail.gmail.com> |
On Wed, Jul 22, 2026 at 3:28 PM Dmitry Osipenko <[email protected]> wrote: > > Depending on firmware, part of the MFG domains may be left ON at boot > leaving only some MFG cores powered, to let the ACP to prefetch the GPU > region when the display controller is brought up. This doesn't play well > with an eventual delay in probing Panfrost when the display controller is > fully set up, as that would make genpd's sync_state() to power off the > domain while ACP tries to prefetch: this is causing an AXI stall, > effectively freezing the AP indefinitely. In order to prevent this from I haven't made any detailed investigation, but to me, it sounds like there is a missing consumer somewhere. Should the ACP/panfrost devices be a consumer of the MFG domains as well? Or perhaps, if the ACP/panfrost should rely on the display controller to be probed and powered-on, to be able to probe? > happening, the sync_state() functionality must be obliterated on all of > the MFG domains: while this guarantees a power leakage if the bootloader > boots the kernel with MFG PDs partially powered on, this is the only way > to ensure stable operation of the SoC during boot on devices with such > firmware because, of course, those will never officially receive a > firmware update. > > Fixes Kappa Chromebook hanging during system boot. > > Fixes: 0e789b491ba0 ("pmdomain: core: Leave powered-on genpds on until sync_state") > Fixes: 13a4b7fb6260 ("pmdomain: core: Leave powered-on genpds on until late_initcall_sync") > Signed-off-by: Dmitry Osipenko <[email protected]> Kind regards Uffe > --- > drivers/pmdomain/mediatek/mt8183-pm-domains.h | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/pmdomain/mediatek/mt8183-pm-domains.h b/drivers/pmdomain/mediatek/mt8183-pm-domains.h > index 3742782a2702..5e33b8628e85 100644 > --- a/drivers/pmdomain/mediatek/mt8183-pm-domains.h > +++ b/drivers/pmdomain/mediatek/mt8183-pm-domains.h > @@ -47,7 +47,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = 0, > .sram_pdn_ack_bits = 0, > - .caps = MTK_SCPD_DOMAIN_SUPPLY, > + .caps = MTK_SCPD_DOMAIN_SUPPLY | MTK_SCPD_KEEP_DEFAULT_OFF, > }, > [MT8183_POWER_DOMAIN_MFG] = { > .name = "mfg", > @@ -57,7 +57,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > - .caps = MTK_SCPD_DOMAIN_SUPPLY, > + .caps = MTK_SCPD_DOMAIN_SUPPLY | MTK_SCPD_KEEP_DEFAULT_OFF, > }, > [MT8183_POWER_DOMAIN_MFG_CORE0] = { > .name = "mfg_core0", > @@ -67,6 +67,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > }, > [MT8183_POWER_DOMAIN_MFG_CORE1] = { > .name = "mfg_core1", > @@ -76,6 +77,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > }, > [MT8183_POWER_DOMAIN_MFG_2D] = { > .name = "mfg_2d", > @@ -85,6 +87,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > .bp_cfg = { > BUS_PROT_WR(INFRA, > MT8183_TOP_AXI_PROT_EN_1_MFG, > -- > 2.54.0 >