[PATCH v2] arm64: dts: mediatek: mt8390-genio-common: add boot phase tags

U-Boot SPL runs after the platform DDR loader has initialized DRAM on
the Genio 510 and Genio 700 EVKs. It needs the debug UART and eMMC
controller, together with their clock, syscon, pinctrl, interrupt and
watchdog providers, to load the firmware FIT.

Mark the nodes consumed by the current SPL configuration with
'bootph-pre-ram' so that the canonical devicetree carries the boot-phase
information and bootloaders do not need local overrides.

Signed-off-by: Carlo Caione <[email protected]>
---
Add the boot-phase annotations needed by U-Boot SPL on the MediaTek
Genio 510 and Genio 700 EVKs. Both boards use the same pre-RAM device
dependency chain, so keep the annotations in their shared
mt8390-genio-common.dtsi.
---
Changes in v2:
- Move the tags from the Genio 700 board DTS to
  mt8390-genio-common.dtsi so they are shared with Genio 510.
- Update the subject and description to cover both EVKs.
- Link to v1: https://patch.msgid.link/20260721-ccaione-upstream-mt8390-bootph-v1-1-5642198f979d@baylibre.com
---
 .../boot/dts/mediatek/mt8390-genio-common.dtsi     | 84 ++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
index b0c97930a0e6..6172160ea9f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
@@ -20,6 +20,10 @@
 #include <dt-bindings/usb/pd.h>
 
 / {
+	memory@40000000 {
+		bootph-pre-ram;
+	};
+
 	aliases {
 		dsi0 = &disp_dsi0;
 		ethernet0 = &eth;
@@ -1586,3 +1590,83 @@ &xhci2 {
 	vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */
 	status = "okay";
 };
+
+&apmixedsys {
+	bootph-pre-ram;
+};
+
+&clk26m {
+	bootph-pre-ram;
+};
+
+&gic {
+	bootph-pre-ram;
+};
+
+&infracfg_ao {
+	bootph-pre-ram;
+};
+
+&mmc0 {
+	bootph-pre-ram;
+};
+
+&mmc0_default_pins {
+	bootph-pre-ram;
+
+	pins-clk {
+		bootph-pre-ram;
+	};
+
+	pins-cmd-dat {
+		bootph-pre-ram;
+	};
+
+	pins-rst {
+		bootph-pre-ram;
+	};
+};
+
+&mmc0_uhs_pins {
+	bootph-pre-ram;
+
+	pins-clk {
+		bootph-pre-ram;
+	};
+
+	pins-cmd-dat {
+		bootph-pre-ram;
+	};
+
+	pins-ds {
+		bootph-pre-ram;
+	};
+
+	pins-rst {
+		bootph-pre-ram;
+	};
+};
+
+&pio {
+	bootph-pre-ram;
+};
+
+&topckgen {
+	bootph-pre-ram;
+};
+
+&uart0 {
+	bootph-pre-ram;
+};
+
+&uart0_pins {
+	bootph-pre-ram;
+
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&watchdog {
+	bootph-pre-ram;
+};

---
base-commit: 11028ab62899e4191e074ee364c712b77823a9c4
change-id: 20260721-ccaione-upstream-mt8390-bootph-ea7a2444292c

Best regards,
--  
Carlo Caione <[email protected]>