Re: [PATCH v10 03/26] dt-bindings: ufs: mediatek,ufs: Add mt8196 variant

On Thu, 2026-07-30 at 11:48 +0200, Louis-Alexis Eyraud wrote:
> From: Nicolas Frattaroli <[email protected]>
> 
> The MediaTek MT8196 SoC's UFS controller uses a different set of
> supplies.
> It is therefore not compatible with the MT8195.
> 
> While it does have a AVDD09_UFS_1 pin in addition to the AVDD09_UFS
> pin,
> it appears that these two pins are commoned together, as the board
> schematic I have access to uses the same supply for both, and the
> downstream driver does not distinguish between the two supplies
> either.
> 
> Add a compatible for it, and modify the binding correspondingly.
> 
> Signed-off-by: Nicolas Frattaroli <[email protected]>
> Signed-off-by: Louis-Alexis Eyraud <[email protected]>
Reviewed-by: Chaotian Jing <[email protected]>
> ---
>  .../devicetree/bindings/ufs/mediatek,ufs.yaml      | 45
> ++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> index e7e360c59ba5..70164e4e54c5 100644
> --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> @@ -16,6 +16,7 @@ properties:
>        - mediatek,mt8183-ufshci
>        - mediatek,mt8192-ufshci
>        - mediatek,mt8195-ufshci
> +      - mediatek,mt8196-ufshci
>  
>    clocks:
>      minItems: 1
> @@ -131,6 +132,20 @@ allOf:
>          clock-names:
>            minItems: 10
>          avdd09-supply: false
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: mediatek,mt8196-ufshci
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 10
> +        clock-names:
> +          minItems: 10
> +        avdd18-supply: false
> +      required:
> +        - operating-points-v2
>  
>  examples:
>    - |
> @@ -177,3 +192,33 @@ examples:
>  
>          mediatek,ufs-disable-mcq;
>      };
> +  - |
> +    #include <dt-bindings/reset/mediatek,mt8196-resets.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    ufshci@16810000 {
> +        compatible = "mediatek,mt8196-ufshci";
> +        reg = <0x16810000 0x2a00>;
> +        interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
> +
> +        clocks = <&ufs_ao_clk 6>, <&ufs_ao_clk 7>, <&clk26m>,
> <&ufs_ao_clk 3>,
> +                 <&clk26m>, <&ufs_ao_clk 4>, <&ufs_ao_clk 0>,
> +                 <&topckgen 7>, <&ufs_ao_clk 1>, <&ufs_ao_clk 2>;
> +        clock-names = "main", "aes", "tick", "unipro_sysclk",
> +                      "unipro_tick", "unipro_mp_bclk", "tx_symbol",
> +                      "mem_sub", "rx_symbol0", "rx_symbol1";
> +
> +        operating-points-v2 = <&ufs_opp_table>;
> +
> +        phys = <&ufsphy>;
> +
> +        avdd09-supply = <&mt6363_vsram_modem>;
> +        vcc-supply = <&mt6363_vemc>;
> +        vccq-supply = <&mt6363_vufs12>;
> +
> +        resets = <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_UNIPRO>,
> +                 <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_CRYPTO>,
> +                 <&ufs_ao_clk MT8196_UFSAO_RST1_UFSHCI>;
> +        reset-names = "unipro", "crypto", "hci";
> +        mediatek,ufs-disable-mcq;
> +    };
>