Re: [PATCH] pinctrl: airoha: fix wrong value for PCIe reset pin

Linus Walleij <[email protected]> Fri, 7 Aug 2026 20:58:06 +0200

Newsgroups	org.infradead.lists.linux-mediatek,org.kernel.vger.linux-gpio,org.kernel.vger.linux-kernel,org.kernel.vger.stable
Message-ID	<CAD++jL=LLyod-me-wXKznKLhjjGFTmp7x5uF1nCUL7fMTBpONg@mail.gmail.com>

Hi Christian,

On Wed, Aug 5, 2026 at 10:41 AM Christian Marangi <[email protected]> wrote:

> The PCIe reset pin actually require the bit to be set as 0 to work as PCIe
> reset pin. When the bit is set as 1, then the PCIe reset pin act as a GPIO
> for GPIO44, GPIO45 and GPIO46.
>
> Cc: [email protected]
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Christian Marangi <[email protected]>

Is this already fixed in the big Airoha patch set from Mikhail
that I just applied?

If this is *not* fixed in what is currently in my tree I need
a rebased version of this for mainline.

If it *is* fixed in what is currently in my tree, this can be
sent separately to the stable tree as a backport once
Torvalds has pulled my changes.

Yours,
Linus Walleij