[PATCH v3 7/8] arm64: dts: mt8167: Properly describe the SoC watchdog
Luca Leonardo Scorcia <[email protected]>
| Newsgroups | org.infradead.lists.linux-mediatek,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-watchdog |
|---|---|
| Message-ID | <[email protected]> |
Currently mt8167 inherits its watchdog from the included mt8516 dtsi, which in turn falls back on mt6589-wdt. However according to the data sheet mt8167 has 15 sw resets instead of 12, and the reset bits are different from mt6589. Use the dedicated mediatek,mt8167-wdt compatible for the watchdog driver, as it correctly describes the SoC resets. Signed-off-by: Luca Leonardo Scorcia <[email protected]> --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 27cf32d7ae35..edfffe35ec14 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8167-clk.h> #include <dt-bindings/memory/mt8167-larb-port.h> #include <dt-bindings/power/mt8167-power.h> +#include <dt-bindings/reset/mediatek,mt8167-resets.h> #include "mt8167-pinfunc.h" @@ -95,6 +96,13 @@ power-domain@MT8167_POWER_DOMAIN_CONN { }; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8167-wdt"; + reg = <0 0x10007000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + pio: pinctrl@1000b000 { compatible = "mediatek,mt8167-pinctrl"; reg = <0 0x1000b000 0 0x1000>; -- 2.43.0