Re: [PATCH v5 0/2] PCI: mediatek-gen3: Add 2-lanes mode support + clock
Chen-Yu Tsai <[email protected]>
| Newsgroups | org.infradead.lists.linux-mediatek,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
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| Message-ID | <CAGXv+5GNvV0yfX2v7E9HxvFpm0xwhGMQLjec=_xV_6YipXFcbw@mail.gmail.com> |
On Fri, Aug 7, 2026 at 11:21 PM Bjorn Helgaas <[email protected]> wrote: > > On Fri, Aug 07, 2026 at 11:24:09AM +0800, Chen-Yu Tsai wrote: > > On Fri, Aug 7, 2026 at 12:53 AM Christian Marangi <[email protected]> wrote: > > > This small series introduce support for 2-lanes mode for Airoha AN7581 > > > > Just a nitpick, but I would probably name this something else, like > > "cross-controller lane-bonding mode" or "lane stealing"? PCIe already > > has 2x lanes as a standard feature, so this naming is a bit confusing. > > It's not like dual-LVDS display in which LVDS is only a single lane. > > I suggested the "2-lane" and "x2" terminology because I assumed the > result is what the PCIe spec would describe as a "x2 Link" consisting > of two Lanes. > > If that's not the case, maybe "cross-controller lane-bonding mode" or > "lane stealing" would be more accurate, but I don't know what those > mean, so if we use them I would also like to know what the result > looks like in standard PCIe terms. Benjamin pointed out later in the thread that it is just bifurcation. I would assume "PCIe bifurcation" is a standard term, so maybe we could call this "Support un-bifurcated 2-lane operation"? On the implementation side, having to reach into the second PCIe controller is a bit messy :( ChenYu > > > SoC. This is needed for correctly functionality of Eagle WiFi Card > > > normally attached to this SoC that require a 2-line PCIe card to > > > correctly work (and give the proper performance) > > > > > > The first 2 patch address a limitation of the PCIe implementation > > > where the PERSTOUT reset were indirectly asserted and deasserted > > > all at the same time (for all the 3 PCIe card) with PCIe > > > enable and disable. > > > The 2 patch address this and introduce correct reset to control > > > reset line for the relevant PCIe line. > > > > > > The last 2 patch add additional logic and support to assert > > > and deassert the PERSTOUT and also apply the required configuration > > > for 2-lanes mode. > > > > > > 2-lanes mode is implemented in DT by adding the required property > > > and by defining the "num-lanes" to 2.