Re: [PATCH v8] net: airoha: npu: use cacheline-sized buffers for mailbox DMA

On Thu, 20 Aug 2026 10:20:08 +0200 Daniel Pawlik wrote:
> size=24 < cache_line=64 fails this regardless of address alignment.
> The swiotlb sync code itself is fine, but the NPU cannot DMA-write to
> the bounce buffer address range (it reads commands fine, never writes
> responses back). This is probably an EN7581 platform limitation.

Sure, that's pretty much what GPT told us some revisions ago.
The question is why.