[PATCH 0/4] rawnand: pl35x: Implement mixed ECC

Hi all,

This series addresses the PL353 errata "SLC ECC misses single error to
bit0 byte0 and fails to detect some double error cases" (see 721059 in
[1]).

The ECC HW engine is known to be broken on this chip, it fails to detect
some bitflips on reads.

This series implements a mixed-ECC where the HW engine is used on writes
and reads are done by software. To make it work, the software ECC has to
use the same layout for the ECC bits than the HW engine. Patches 1 & 2
add the PL35x ordering to the available orderings for soft ECC. Patches
3 & 4 make use of this ordering to implement the mixed-ECC for the PL353
controller.

Note that this series is based on top of nand/next.

[1]: https://developer.arm.com/documentation/rlnc000227/a

Signed-off-by: Bastien Curutchet <[email protected]>
---
Bastien Curutchet (4):
      nand: hamming: Replace sm_order boolean with enum
      nand: hamming: Add support for the PL35x ECC bit ordering
      rawnand: base: Export nand_read_page_swecc
      rawnand: pl35x: Implement mixed ECC computing

 drivers/mtd/nand/ecc-sw-hamming.c            | 179 ++++++++++++++++++---------
 drivers/mtd/nand/raw/nand_base.c             |  11 +-
 drivers/mtd/nand/raw/pl35x-nand-controller.c | 173 ++------------------------
 include/linux/mtd/nand-ecc-sw-hamming.h      |  20 ++-
 include/linux/mtd/rawnand.h                  |   7 +-
 5 files changed, 161 insertions(+), 229 deletions(-)
---
base-commit: f97bdc8ec1dc7b33781a702eeba55326c206be56
change-id: 20260529-mix-ecc-46e8ccd4e9ae

Best regards,
-- 
Bastien Curutchet <[email protected]>


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