Re: [PATCH v2 0/3] mtd: rawnand: sunxi: fix H6/H616 controller timings

On Fri, Aug 7, 2026 at 7:58 AM Miquel Raynal <[email protected]> wrote:
>
> Hi James,
>
> On 17/07/2026 at 11:33:56 -06, James Hilliard <[email protected]> wrote:
>
> > The sunxi NAND timing solver currently applies the original A10 NDFC
> > timing characteristics to every supported controller. The H6/H616 NDFC
> > uses two internal cycles for several setup and hold intervals and has
> > different delay-field encodings, so the resulting clock and timing
> > register values do not match the hardware.
> >
> > Prepare for per-controller timing data in two behaviorally focused
> > patches, then add and select the H616 characteristics in the final fix.
> > Legacy controllers retain their existing setup-cycle behavior and delay
> > encodings.
> >
> > Tested on an H616 board with Toshiba TC58NVG1S3H NAND.
> >
> > Signed-off-by: James Hilliard <[email protected]>
>
> There are a number of checkpatch issue. Can you please fix them? (except
> the camelcase one which is fine with timing names coming from the ONFI
> spec).

Should be fixed in my v3:
https://lore.kernel.org/all/20260807-submit-sunxi-nand-h6-h616-timings-v3-0-91287b543f41@gmail.com/

>
> Thanks,
> Miquèl

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