Re: [PATCH v1 1/1] nvme-pci: adaptive interrupt coalescing

On Wed, Jul 22, 2026 at 10:22:11AM +0800, changfengnan wrote:
> 
> > From: "Keith Busch"<[email protected]>
> > Date:  Tue, Jul 21, 2026, 23:11
> > Subject:  Re: [PATCH v1 1/1] nvme-pci: adaptive interrupt coalescing
> > To: "Fengnan Chang"<[email protected]>
> > Cc: <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>
> > On Tue, Jul 21, 2026 at 04:37:39PM +0800, Fengnan Chang wrote:
> > > @@ -1618,6 +1748,8 @@ static inline bool nvme_poll_cq(struct nvme_queue *nvmeq,
> > >                   * the cqe requires a full read memory barrier
> > >                   */
> > >                  dma_rmb();
> > > +                if (sq_head)
> > > +                        *sq_head = le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].sq_head);
> > 
> > This is the wrong criteria to determine the outstanding depth. The spec
> > allows the controller to move this forward after it has read an entry.
> > The commands may still be in progress, so the depth of future
> > completions to expect can't depend on this value.
> > 
> > But in general, I agree with the spirit of where this is going.
> 
> Thanks for your feedback.  I’d like to hear more opinions from others. 
> If this is the right direction, I’ll continue to improve this patch.
> 
> Hi Jens, Christoph, Sagi: 
> what do you think?

Yes, this is a useful idea, please continue with it if you can.