Re: [PATCH v5 01/10] phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc

On Thu, Jul 23, 2026 at 10:41:44PM +0300, Cristian Ciocaltea wrote:
> The PHY PLL can be programmed by an external component, e.g. the
> bootloader, just before the recalc_rate() callback is invoked during
> devm_clk_hw_register() in the probe path.
> 
> Therefore rk_hdptx_phy_clk_recalc_rate() finds the PLL enabled and
> attempts to compute the clock rate, while making use of the bpc value
> from the HDMI PHY configuration, which always defaults to 8 because
> phy_configure() was not run at that point.  As a consequence, the
> (re)calculated rate is incorrect when the actual bpc was higher than 8.
> 
> Do not rely on any of the hdmi_cfg members when computing the clock rate
> and, instead, read the required input data (i.e. bpc), directly from the
> hardware registers.
> 
> Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from PLL config")
> Tested-by: Thomas Niederprüm <[email protected]>
> Tested-by: Simon Wright <[email protected]>
> Tested-by: Diederik de Haas <[email protected]>  # NanoPC-T6 LTS
> Reviewed-by: Andy Yan <[email protected]>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Signed-off-by: Cristian Ciocaltea <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

- Mani

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